mirror of https://github.com/pvnis/srsRAN_4G.git
rework scheduler
Francisco Paisana
6 years ago
committed by
Andre Puschmann
parent
2aa36dd11c
commit
7be183c223
@ -0,0 +1,152 @@
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/*
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* Copyright 2013-2019 Software Radio Systems Limited
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*
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* This file is part of srsLTE.
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*
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* srsLTE is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Affero General Public License as
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* published by the Free Software Foundation, either version 3 of
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* the License, or (at your option) any later version.
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*
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* srsLTE is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Affero General Public License for more details.
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*
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* A copy of the GNU Affero General Public License can be found in
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* the LICENSE file in the top-level directory of this distribution
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* and at http://www.gnu.org/licenses/.
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*
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*/
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#ifndef SRSLTE_SCHEDULER_GRID_H
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#define SRSLTE_SCHEDULER_GRID_H
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#include "lib/include/srslte/interfaces/sched_interface.h"
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#include "srsenb/hdr/mac/scheduler_ue.h"
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#include "srslte/common/bounded_bitset.h"
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#include "srslte/common/log.h"
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#include <vector>
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namespace srsenb {
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// Type of Allocation
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enum class alloc_type_t { DL_BC, DL_PCCH, DL_RAR, DL_DATA, UL_DATA };
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// Result of alloc attempt
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struct alloc_outcome_t {
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enum result_enum { SUCCESS, DCI_COLLISION, RB_COLLISION, ERROR };
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result_enum result = ERROR;
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alloc_outcome_t() = default;
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alloc_outcome_t(result_enum e) : result(e) {}
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operator result_enum() { return result; }
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operator bool() { return result == SUCCESS; }
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const char* to_string() const;
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};
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class pdcch_grid_t
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{
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public:
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struct alloc_t {
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uint16_t rnti;
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srslte_dci_location_t dci_pos = {0, 0};
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pdcch_mask_t current_mask;
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pdcch_mask_t total_mask;
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};
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typedef std::vector<const alloc_t*> alloc_result_t;
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void init(srslte::log* log_,
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srslte_regs_t* regs,
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sched_ue::sched_dci_cce_t* common_locs,
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sched_ue::sched_dci_cce_t (*rar_locs)[10]);
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void new_tti(uint32_t tti_rx_, uint32_t start_cfi);
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bool alloc_dci(alloc_type_t alloc_type, uint32_t aggr_idx, sched_ue* user = NULL);
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bool set_cfi(uint32_t cfi);
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// getters
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uint32_t get_cfi() const { return current_cfix + 1; }
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void get_allocs(alloc_result_t* vec = nullptr, pdcch_mask_t* tot_mask = nullptr, size_t idx = 0) const;
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uint32_t nof_cces() const { return cce_size_array[current_cfix]; }
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size_t nof_allocs() const { return nof_dci_allocs; }
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size_t nof_alloc_combinations() const { return prev_end - prev_start; }
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void print_result(bool verbose = false) const;
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uint32_t get_sf_idx() const { return sf_idx; }
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private:
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const static uint32_t nof_cfis = 3;
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typedef std::pair<int, alloc_t> tree_node_t;
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void reset();
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const sched_ue::sched_dci_cce_t* get_cce_loc_table(alloc_type_t alloc_type, sched_ue* user) const;
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void update_alloc_tree(int node_idx,
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uint32_t aggr_idx,
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sched_ue* user,
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alloc_type_t alloc_type,
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const sched_ue::sched_dci_cce_t* dci_locs);
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// consts
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srslte::log* log_h = nullptr;
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sched_ue::sched_dci_cce_t* common_locations = nullptr;
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sched_ue::sched_dci_cce_t* rar_locations[10];
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uint32_t cce_size_array[nof_cfis];
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// tti vars
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uint32_t tti_rx;
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uint32_t sf_idx;
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uint32_t current_cfix;
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size_t prev_start, prev_end;
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std::vector<tree_node_t> dci_alloc_tree;
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size_t nof_dci_allocs;
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};
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class tti_grid_t
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{
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public:
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typedef std::pair<alloc_outcome_t, rbg_range_t> ctrl_alloc_t;
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void init(srslte::log* log_, sched_interface::cell_cfg_t* cell_, const pdcch_grid_t& pdcch_grid);
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void new_tti(uint32_t tti_rx_, uint32_t start_cfi);
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ctrl_alloc_t alloc_dl_ctrl(uint32_t aggr_lvl, alloc_type_t alloc_type);
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alloc_outcome_t alloc_dl_data(sched_ue* user, const rbgmask_t& user_mask);
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alloc_outcome_t alloc_ul_data(sched_ue* user, ul_harq_proc::ul_alloc_t alloc, bool needs_pdcch);
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// getters
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uint32_t get_avail_rbgs() const { return avail_rbg; }
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rbgmask_t& get_dl_mask() { return dl_mask; }
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const rbgmask_t& get_dl_mask() const { return dl_mask; }
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prbmask_t& get_ul_mask() { return ul_mask; }
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const prbmask_t& get_ul_mask() const { return ul_mask; }
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uint32_t get_cfi() const { return pdcch_alloc.get_cfi(); }
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const pdcch_grid_t& get_pdcch_grid() const { return pdcch_alloc; }
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uint32_t get_tti_rx() const { return tti_rx; }
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uint32_t get_tti_tx_dl() const { return tti_tx_dl; }
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uint32_t get_tti_tx_ul() const { return tti_tx_ul; }
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uint32_t get_sfn() const { return sfn; }
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uint32_t get_sf_idx() const { return pdcch_alloc.get_sf_idx(); }
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private:
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alloc_outcome_t alloc_dl(uint32_t aggr_lvl, alloc_type_t alloc_type, rbgmask_t alloc_mask, sched_ue* user = NULL);
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// consts
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srslte::log* log_h = nullptr;
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sched_interface::cell_cfg_t* cell_cfg = nullptr;
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uint32_t nof_prbs;
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uint32_t nof_rbgs;
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uint32_t si_n_rbg, rar_n_rbg;
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// tti const
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uint32_t tti_rx = 10241;
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// derived
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uint32_t tti_tx_dl, tti_tx_ul;
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uint32_t sfn;
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pdcch_grid_t pdcch_alloc;
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// internal state
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uint32_t avail_rbg = 0;
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rbgmask_t dl_mask;
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prbmask_t ul_mask;
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};
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} // namespace srsenb
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#endif // SRSLTE_SCHEDULER_GRID_H
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,369 @@
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/*
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* Copyright 2013-2019 Software Radio Systems Limited
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*
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* This file is part of srsLTE.
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*
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* srsLTE is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Affero General Public License as
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* published by the Free Software Foundation, either version 3 of
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* the License, or (at your option) any later version.
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*
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* srsLTE is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Affero General Public License for more details.
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*
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* A copy of the GNU Affero General Public License can be found in
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* the LICENSE file in the top-level directory of this distribution
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* and at http://www.gnu.org/licenses/.
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*
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*/
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#include "srsenb/hdr/mac/scheduler_grid.h"
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#include "srsenb/hdr/mac/scheduler.h"
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#include <srslte/interfaces/sched_interface.h>
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namespace srsenb {
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const char* alloc_outcome_t::to_string() const
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{
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switch (result) {
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case SUCCESS:
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return "success";
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case DCI_COLLISION:
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return "dci_collision";
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case RB_COLLISION:
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return "rb_collision";
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case ERROR:
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return "error";
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}
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return "unknown error";
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}
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/*******************************************************
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* PDCCH Allocation Methods
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*******************************************************/
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void pdcch_grid_t::init(srslte::log* log_,
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srslte_regs_t* regs,
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sched_ue::sched_dci_cce_t* common_locs,
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sched_ue::sched_dci_cce_t (*rar_locs)[10])
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{
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log_h = log_;
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common_locations = common_locs;
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for (uint32_t cfix = 0; cfix < 3; ++cfix) {
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rar_locations[cfix] = rar_locs[cfix];
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}
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// precompute nof_cces
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for (uint32_t cfix = 0; cfix < nof_cfis; ++cfix) {
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int ret = srslte_regs_pdcch_ncce(regs, cfix + 1);
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if (ret < 0) {
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log_h->error("SCHED: Failed to calculate the number of CCEs in the PDCCH\n");
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}
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cce_size_array[cfix] = (uint32_t)ret;
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}
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reset();
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}
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void pdcch_grid_t::new_tti(uint32_t tti_rx_, uint32_t start_cfi)
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{
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tti_rx = tti_rx_;
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sf_idx = TTI_TX(tti_rx) % 10;
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current_cfix = start_cfi - 1;
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reset();
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}
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const sched_ue::sched_dci_cce_t* pdcch_grid_t::get_cce_loc_table(alloc_type_t alloc_type, sched_ue* user) const
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{
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switch (alloc_type) {
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case alloc_type_t::DL_BC:
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return &common_locations[current_cfix];
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case alloc_type_t::DL_PCCH:
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return &common_locations[current_cfix];
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case alloc_type_t::DL_RAR:
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return &rar_locations[current_cfix][sf_idx];
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case alloc_type_t::DL_DATA:
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return user->get_locations(current_cfix + 1, sf_idx);
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case alloc_type_t::UL_DATA:
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return user->get_locations(current_cfix + 1, sf_idx);
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}
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return NULL;
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}
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bool pdcch_grid_t::alloc_dci(alloc_type_t alloc_type, uint32_t aggr_idx, sched_ue* user)
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{
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// FIXME: Make the alloc tree update lazy
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/* Get DCI Location Table */
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const sched_ue::sched_dci_cce_t* dci_locs = get_cce_loc_table(alloc_type, user);
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if (!dci_locs) {
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return false;
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}
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/* Search for potential DCI positions */
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if (prev_end > 0) {
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for (size_t j = prev_start; j < prev_end; ++j) {
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update_alloc_tree((int)j, aggr_idx, user, alloc_type, dci_locs);
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}
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} else {
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update_alloc_tree(-1, aggr_idx, user, alloc_type, dci_locs);
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}
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// if no pdcch space was available
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if (dci_alloc_tree.size() == prev_end) {
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return false;
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}
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prev_start = prev_end;
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prev_end = dci_alloc_tree.size();
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nof_dci_allocs++;
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return true;
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}
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void pdcch_grid_t::update_alloc_tree(int parent_node_idx,
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uint32_t aggr_idx,
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sched_ue* user,
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alloc_type_t alloc_type,
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const sched_ue::sched_dci_cce_t* dci_locs)
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{
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alloc_t alloc;
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alloc.rnti = (user != nullptr) ? user->get_rnti() : (uint16_t)0u;
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alloc.dci_pos.L = aggr_idx;
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// get cumulative pdcch mask
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pdcch_mask_t cum_mask;
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if (parent_node_idx >= 0) {
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cum_mask = dci_alloc_tree[parent_node_idx].second.total_mask;
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} else {
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cum_mask.resize(nof_cces());
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}
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uint32_t nof_locs = dci_locs->nof_loc[aggr_idx];
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for (uint32_t i = 0; i < nof_locs; ++i) {
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uint32_t startpos = dci_locs->cce_start[aggr_idx][i];
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if (alloc_type == alloc_type_t::DL_DATA and user->pucch_sr_collision(TTI_TX(tti_rx), startpos)) {
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// will cause a collision in the PUCCH
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continue;
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}
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pdcch_mask_t alloc_mask(nof_cces());
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alloc_mask.fill(startpos, startpos + (1u << aggr_idx));
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if ((cum_mask & alloc_mask).any()) {
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// there is collision. Try another mask
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continue;
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}
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// Allocation successful
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alloc.current_mask = alloc_mask;
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alloc.total_mask = cum_mask | alloc_mask;
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alloc.dci_pos.ncce = startpos;
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// Prune if repetition
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uint32_t j = prev_end;
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for (; j < dci_alloc_tree.size(); ++j) {
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if (dci_alloc_tree[j].second.total_mask == alloc.total_mask) {
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break;
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}
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}
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if (j < dci_alloc_tree.size()) {
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continue;
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}
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// Register allocation
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dci_alloc_tree.emplace_back(parent_node_idx, alloc);
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}
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}
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bool pdcch_grid_t::set_cfi(uint32_t cfi)
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{
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current_cfix = cfi - 1;
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// FIXME: use this function for dynamic cfi
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// FIXME: The estimation of the number of required prbs in metric depends on CFI. Analyse the consequences
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return true;
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}
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void pdcch_grid_t::reset()
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{
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prev_start = 0;
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prev_end = 0;
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dci_alloc_tree.clear();
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nof_dci_allocs = 0;
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}
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void pdcch_grid_t::get_allocs(alloc_result_t* vec, pdcch_mask_t* tot_mask, size_t idx) const
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{
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// if alloc tree is empty
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if (prev_start == prev_end) {
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if (vec)
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vec->clear();
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if (tot_mask) {
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tot_mask->reset();
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}
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return;
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}
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// set vector of allocations
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if (vec) {
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vec->clear();
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size_t i = prev_start + idx;
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while (dci_alloc_tree[i].first >= 0) {
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vec->push_back(&dci_alloc_tree[i].second);
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i = (size_t)dci_alloc_tree[i].first;
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}
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vec->push_back(&dci_alloc_tree[i].second);
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std::reverse(vec->begin(), vec->end());
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}
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// set final cce mask
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if (tot_mask) {
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*tot_mask = dci_alloc_tree[prev_start + idx].second.total_mask;
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}
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}
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void pdcch_grid_t::print_result(bool verbose) const
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{
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if (prev_start == prev_end) {
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log_h->info("SCHED: No DCI allocations\n");
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}
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std::stringstream ss;
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ss << "SCHED: cfi=" << get_cfi() << ", " << prev_end - prev_start << " DCI allocation combinations:\n";
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// get all the possible combinations of DCI allocations
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uint32_t count = 0;
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for (size_t i = prev_start; i < prev_end; ++i) {
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alloc_result_t vec;
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pdcch_mask_t tot_mask;
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get_allocs(&vec, &tot_mask, i - prev_start);
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ss << " combination " << count << ": mask=0x" << tot_mask.to_hex().c_str();
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if (verbose) {
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ss << ", DCI allocs:\n";
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for (const auto& dci_alloc : vec) {
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char hex[5];
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sprintf(hex, "%x", dci_alloc->rnti);
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ss << " > rnti=0x" << hex << ": " << dci_alloc->current_mask.to_hex().c_str() << " / "
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<< dci_alloc->total_mask.to_hex().c_str() << "\n";
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}
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} else {
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ss << "\n";
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}
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count++;
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}
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log_h->info("%s", ss.str().c_str());
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}
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/*******************************************************
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* TTI resource Scheduling Methods
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*******************************************************/
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void tti_grid_t::init(srslte::log* log_, sched_interface::cell_cfg_t* cell_, const pdcch_grid_t& pdcch_grid)
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{
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log_h = log_;
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cell_cfg = cell_;
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nof_prbs = cell_cfg->cell.nof_prb;
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uint32_t P = srslte_ra_type0_P(cell_cfg->cell.nof_prb);
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nof_rbgs = srslte::ceil_div(cell_cfg->cell.nof_prb, P);
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si_n_rbg = srslte::ceil_div(4, P);
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rar_n_rbg = srslte::ceil_div(3, P);
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pdcch_alloc = pdcch_grid;
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}
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void tti_grid_t::new_tti(uint32_t tti_rx_, uint32_t start_cfi)
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{
|
||||
tti_rx = tti_rx_;
|
||||
|
||||
// derived
|
||||
tti_tx_dl = TTI_TX(tti_rx);
|
||||
tti_tx_ul = TTI_RX_ACK(tti_rx);
|
||||
sfn = tti_tx_dl / 10;
|
||||
|
||||
// internal state
|
||||
avail_rbg = nof_rbgs;
|
||||
dl_mask.reset();
|
||||
dl_mask.resize(nof_rbgs);
|
||||
ul_mask.reset();
|
||||
ul_mask.resize(nof_prbs);
|
||||
pdcch_alloc.new_tti(tti_rx, start_cfi);
|
||||
}
|
||||
|
||||
alloc_outcome_t tti_grid_t::alloc_dl(uint32_t aggr_lvl, alloc_type_t alloc_type, rbgmask_t alloc_mask, sched_ue* user)
|
||||
{
|
||||
// Check RBG collision
|
||||
if ((dl_mask & alloc_mask).any()) {
|
||||
return alloc_outcome_t::RB_COLLISION;
|
||||
}
|
||||
|
||||
// Allocate DCI in PDCCH
|
||||
if (not pdcch_alloc.alloc_dci(alloc_type, aggr_lvl, user)) {
|
||||
return alloc_outcome_t::DCI_COLLISION;
|
||||
}
|
||||
|
||||
// Allocate RBGs
|
||||
dl_mask |= alloc_mask;
|
||||
avail_rbg -= alloc_mask.count();
|
||||
|
||||
return alloc_outcome_t::SUCCESS;
|
||||
}
|
||||
|
||||
tti_grid_t::ctrl_alloc_t tti_grid_t::alloc_dl_ctrl(uint32_t aggr_lvl, alloc_type_t alloc_type)
|
||||
{
|
||||
rbg_range_t range;
|
||||
range.rbg_start = nof_rbgs - avail_rbg;
|
||||
range.rbg_end = range.rbg_start + ((alloc_type == alloc_type_t::DL_RAR) ? rar_n_rbg : si_n_rbg);
|
||||
|
||||
if (alloc_type != alloc_type_t::DL_RAR and alloc_type != alloc_type_t::DL_BC and
|
||||
alloc_type != alloc_type_t::DL_PCCH) {
|
||||
log_h->error("SCHED: DL control allocations must be RAR/BC/PDCCH\n");
|
||||
return {alloc_outcome_t::ERROR, range};
|
||||
}
|
||||
// Setup range starting from left
|
||||
if (range.rbg_end > nof_rbgs) {
|
||||
return {alloc_outcome_t::RB_COLLISION, range};
|
||||
}
|
||||
|
||||
// allocate DCI and RBGs
|
||||
rbgmask_t new_mask(dl_mask.size());
|
||||
new_mask.fill(range.rbg_start, range.rbg_end);
|
||||
return {alloc_dl(aggr_lvl, alloc_type, new_mask), range};
|
||||
}
|
||||
|
||||
alloc_outcome_t tti_grid_t::alloc_dl_data(sched_ue* user, const rbgmask_t& user_mask)
|
||||
{
|
||||
srslte_dci_format_t dci_format = user->get_dci_format();
|
||||
uint32_t aggr_level = user->get_aggr_level(srslte_dci_format_sizeof(&cell_cfg->cell, NULL, NULL, dci_format));
|
||||
return alloc_dl(aggr_level, alloc_type_t::DL_DATA, user_mask, user);
|
||||
}
|
||||
|
||||
alloc_outcome_t tti_grid_t::alloc_ul_data(sched_ue* user, ul_harq_proc::ul_alloc_t alloc, bool needs_pdcch)
|
||||
{
|
||||
if (alloc.RB_start + alloc.L > ul_mask.size()) {
|
||||
return alloc_outcome_t::ERROR;
|
||||
}
|
||||
|
||||
prbmask_t newmask(ul_mask.size());
|
||||
newmask.fill(alloc.RB_start, alloc.RB_start + alloc.L);
|
||||
if ((ul_mask & newmask).any()) {
|
||||
return alloc_outcome_t::RB_COLLISION;
|
||||
}
|
||||
|
||||
// Generate PDCCH except for RAR and non-adaptive retx
|
||||
if (needs_pdcch) {
|
||||
uint32_t aggr_idx = user->get_aggr_level(srslte_dci_format_sizeof(&cell_cfg->cell, NULL, NULL, SRSLTE_DCI_FORMAT0));
|
||||
if (not pdcch_alloc.alloc_dci(alloc_type_t::UL_DATA, aggr_idx, user)) {
|
||||
return alloc_outcome_t::DCI_COLLISION;
|
||||
}
|
||||
}
|
||||
|
||||
ul_mask |= newmask;
|
||||
|
||||
return alloc_outcome_t::SUCCESS;
|
||||
}
|
||||
|
||||
} // namespace srsenb
|
||||
Loading…
Reference in New Issue