feature,sched: allow setting initial DL CQI in enb.conf

master
Francisco 4 years ago committed by Francisco Paisana
parent 4cf5a8b25a
commit 6ababf401b

@ -59,7 +59,6 @@ struct cell_cfg_t {
double ul_freq_hz;
int target_pucch_sinr_db;
int target_pusch_sinr_db;
uint32_t initial_dl_cqi;
bool enable_phr_handling;
int min_phr_thres;
asn1::rrc::mob_ctrl_info_s::t304_e_ t304;

@ -64,6 +64,7 @@ public:
uint32_t min_tpc_tti_interval = 1;
float ul_snr_avg_alpha = 0.05;
int init_ul_snr_value = 5;
int init_dl_cqi = 5;
};
struct cell_cfg_t {
@ -100,7 +101,6 @@ public:
uint32_t nrb_cqi;
uint32_t ncs_an;
uint32_t initial_dl_cqi;
uint32_t srs_subframe_config;
uint32_t srs_subframe_offset;

@ -176,6 +176,7 @@ enable = false
# min_tpc_tti_interval: Minimum TTI interval between TPCs different than 1
# ul_snr_avg_alpha: Exponential Average alpha coefficient used in estimation of UL SNR
# init_ul_snr_value: Initial UL SNR value used for computing MCS in the first UL grant
# init_dl_cqi: DL CQI value used before any CQI report is available to the eNB
#
#####################################################################
[scheduler]
@ -198,6 +199,7 @@ enable = false
#min_tpc_tti_interval = 1
#ul_snr_avg_alpha=0.05
#init_ul_snr_value=5
#init_dl_cqi=5
#####################################################################
# eMBMS configuration options

@ -758,7 +758,6 @@ static int parse_cell_list(all_args_t* args, rrc_cfg_t* rrc_cfg, Setting& root)
parse_default_field(cell_cfg.ul_earfcn, cellroot, "ul_earfcn", 0u); // will be derived from DL EARFCN If not set
parse_default_field(
cell_cfg.root_seq_idx, cellroot, "root_seq_idx", rrc_cfg->sibs[1].sib2().rr_cfg_common.prach_cfg.root_seq_idx);
parse_default_field(cell_cfg.initial_dl_cqi, cellroot, "initial_dl_cqi", 5u);
parse_default_field(cell_cfg.meas_cfg.meas_gap_period, cellroot, "meas_gap_period", 0u);
if (cellroot.exists("meas_gap_offset_subframe")) {
cell_cfg.meas_cfg.meas_gap_offset_subframe.resize(cellroot["meas_gap_offset_subframe"].getLength());

@ -158,6 +158,7 @@ void parse_args(all_args_t* args, int argc, char* argv[])
("scheduler.min_tpc_tti_interval", bpo::value<uint32_t>(&args->stack.mac.sched.min_tpc_tti_interval)->default_value(1), "Minimum TTI interval between positive or negative TPCs")
("scheduler.ul_snr_avg_alpha", bpo::value<float>(&args->stack.mac.sched.ul_snr_avg_alpha)->default_value(0.05), "Exponential Average alpha coefficient used in estimation of UL SNR")
("scheduler.init_ul_snr_value", bpo::value<int>(&args->stack.mac.sched.init_ul_snr_value)->default_value(5), "Initial UL SNR value used for computing MCS in the first UL grant")
("scheduler.init_dl_cqi", bpo::value<int>(&args->stack.mac.sched.init_dl_cqi)->default_value(5), "DL CQI value used before any CQI report is available to the eNB")
/* Downlink Channel emulator section */

@ -48,10 +48,8 @@ sched_ue_cell::sched_ue_cell(uint16_t rnti_, const sched_cell_params_t& cell_cfg
fixed_mcs_ul(cell_cfg_.sched_cfg->pusch_mcs),
current_tti(current_tti_),
max_aggr_level(cell_cfg_.sched_cfg->max_aggr_level >= 0 ? cell_cfg_.sched_cfg->max_aggr_level : 3),
dl_cqi_ctxt(cell_cfg_.nof_prb(), 0, 1)
dl_cqi_ctxt(cell_cfg_.nof_prb(), 0, cell_cfg_.sched_cfg->init_dl_cqi)
{
clear_feedback();
float target_bler = cell_cfg->sched_cfg->target_bler;
delta_inc = cell_cfg->sched_cfg->adaptive_link_step_size; // delta_{down} of OLLA
delta_dec = (1 - target_bler) * delta_inc / target_bler;
@ -157,7 +155,7 @@ void sched_ue_cell::clear_feedback()
dl_ri_tti_rx = tti_point{};
dl_pmi = 0;
dl_pmi_tti_rx = tti_point{};
dl_cqi_ctxt.reset_cqi(ue_cc_idx == 0 ? cell_cfg->cfg.initial_dl_cqi : 1);
dl_cqi_ctxt.reset_cqi(ue_cc_idx == 0 ? cell_cfg->sched_cfg->init_dl_cqi : 1);
ul_cqi_tti_rx = tti_point{};
}

@ -646,7 +646,6 @@ void rrc::config_mac()
item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset;
item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx;
item.enable_64qam = cfg.sibs[1].sib2().rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam;
item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi;
item.target_pucch_ul_sinr = cfg.cell_list[ccidx].target_pucch_sinr_db;
item.target_pusch_ul_sinr = cfg.cell_list[ccidx].target_pusch_sinr_db;
item.enable_phr_handling = cfg.cell_list[ccidx].enable_phr_handling;

@ -49,7 +49,6 @@ inline srsenb::sched_interface::cell_cfg_t generate_default_cell_cfg(uint32_t no
cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 4;
cell_cfg.prach_rar_window = 3;
cell_cfg.maxharq_msg3tx = 3;
cell_cfg.initial_dl_cqi = 6;
cell_cfg.target_pusch_ul_sinr = -1;
cell_cfg.target_pucch_ul_sinr = -1;
cell_cfg.enable_phr_handling = false;

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