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@ -11,6 +11,7 @@
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*/
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#include "srsgnb/hdr/stack/mac/sched_nr_signalling.h"
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#include "srsgnb/hdr/stack/mac/sched_nr_grant_allocator.h"
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#define POS_IN_BURST_FIRST_BIT_IDX 0
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#define POS_IN_BURST_SECOND_BIT_IDX 1
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@ -83,23 +84,119 @@ void sched_ssb_basic(const slot_point& sl_point, uint32_t ssb_periodicity, ssb_l
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}
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}
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void sched_dl_signalling(const bwp_params_t& bwp_params,
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slot_point sl_pdcch,
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ssb_list& ssb_list,
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nzp_csi_rs_list& nzp_csi_rs)
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void sched_dl_signalling(bwp_slot_allocator& bwp_alloc)
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{
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const bwp_params_t& bwp_params = bwp_alloc.cfg;
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slot_point sl_pdcch = bwp_alloc.get_pdcch_tti();
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bwp_slot_grid& sl_grid = bwp_alloc.tx_slot_grid();
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srsran_slot_cfg_t cfg;
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cfg.idx = sl_pdcch.to_uint();
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// Schedule SSB
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sched_ssb_basic(sl_pdcch, bwp_params.cell_cfg.ssb.periodicity_ms, ssb_list);
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sched_ssb_basic(sl_pdcch, bwp_params.cell_cfg.ssb.periodicity_ms, sl_grid.dl.phy.ssb);
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// Schedule NZP-CSI-RS
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sched_nzp_csi_rs(bwp_params.cfg.pdsch.nzp_csi_rs_sets, cfg, nzp_csi_rs);
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sched_nzp_csi_rs(bwp_params.cfg.pdsch.nzp_csi_rs_sets, cfg, sl_grid.dl.phy.nzp_csi_rs);
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}
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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bool fill_dci_sib(prb_interval interv, uint32_t sib_id, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci)
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{
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dci.mcs = 5;
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dci.ctx.format = srsran_dci_format_nr_1_0;
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dci.ctx.ss_type = srsran_search_space_type_common_0;
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dci.ctx.rnti_type = srsran_rnti_type_si;
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dci.ctx.rnti = SRSRAN_SIRNTI;
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dci.ctx.coreset_id = 0;
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dci.freq_domain_assigment = srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, interv.start(), interv.length());
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dci.time_domain_assigment = 0;
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dci.tpc = 1;
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dci.bwp_id = bwp_cfg.bwp_id;
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dci.cc_id = bwp_cfg.cc;
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dci.rv = 0;
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dci.sii = sib_id == 1 ? 0 : 1;
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return true;
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}
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si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
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bwp_cfg(&bwp_cfg_), logger(srslog::fetch_basic_logger(bwp_cfg_.sched_cfg.logger_name))
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{}
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void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
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{
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if (true) {
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// CORESET#0 must be present, otherwise SIs are not allocated
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// TODO: provide proper config
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return;
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}
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const uint32_t si_aggr_level = 2;
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slot_point sl_pdcch = bwp_alloc.get_pdcch_tti();
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const prb_bitmap& prbs = bwp_alloc.res_grid()[sl_pdcch].dl_prbs.prbs();
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// SIB1 case
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if (sl_pdcch.to_uint() % 160 == 0) {
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// TODO: compute if SIB1 slot based on config
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const uint32_t aggr_lvl_idx = 2;
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const uint32_t sib_id = 1;
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const uint32_t sib1len = 77; // TODO: extract from config
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alloc_result ret = bwp_alloc.alloc_si(aggr_lvl_idx, sib_id, sib1len, prb_interval{0, 7});
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if (ret != alloc_result::success) {
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bwp_alloc.logger.warning("SCHED: Cannot allocate SIB1.");
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}
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}
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// Update SI windows
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uint32_t N = bwp_cfg->slots.size();
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for (si_msg_ctxt_t& si : pending_sis) {
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uint32_t x = (si.n - 1) * si.win_len;
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if (not si.win_start.valid() and (sl_pdcch.sfn() % si.period == x / N) and
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sl_pdcch.slot_idx() == x % bwp_cfg->slots.size()) {
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// If start of SI message window
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si.win_start = sl_pdcch;
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} else if (si.win_start.valid() and si.win_start + si.win_len >= sl_pdcch) {
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// If end of SI message window
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logger.warning(
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"SCHED: Could not allocate SI message idx=%d, len=%d. Cause: %s", si.n, si.len, to_string(si.result));
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si.win_start.clear();
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}
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}
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// Schedule pending SIs
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if (bwp_cfg->slots[sl_pdcch.slot_idx()].is_dl) {
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for (si_msg_ctxt_t& si : pending_sis) {
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if (not si.win_start.valid()) {
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continue;
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}
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// Schedule SIBs
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// TODO
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// TODO: NOTE 2: The UE is not required to monitor PDCCH monitoring occasion(s) corresponding to each transmitted
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// SSB in SI-window.
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// Attempt grants with increasing number of PRBs (if the number of PRBs is too low, the coderate is invalid)
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si.result = alloc_result::invalid_coderate;
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uint32_t prb_start_idx = 0;
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for (uint32_t nprbs = 4; nprbs < bwp_cfg->cfg.rb_width and si.result == alloc_result::invalid_coderate; ++nprbs) {
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prb_interval grant = find_empty_interval_of_length(prbs, nprbs, prb_start_idx);
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prb_start_idx = grant.start();
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if (grant.length() != nprbs) {
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si.result = alloc_result::no_sch_space;
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break;
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}
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si.result = bwp_alloc.alloc_si(si_aggr_level, si.n, si.n_tx, grant);
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if (si.result == alloc_result::success) {
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// SIB scheduled successfully
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si.win_start.clear();
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si.n_tx++;
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}
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}
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}
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}
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}
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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} // namespace sched_nr_impl
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} // namespace srsenb
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