mirror of https://github.com/pvnis/srsRAN_4G.git
sched,nr: implement NR PDCCH allocation algorithm
Francisco
4 years ago
committed by
Andre Puschmann
parent
a70ad58440
commit
5b3c5ded63
@ -0,0 +1,103 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#ifndef SRSRAN_SCHED_NR_PDCCH_H
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#define SRSRAN_SCHED_NR_PDCCH_H
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#include "srsenb/hdr/stack/mac/nr/sched_nr_common.h"
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#include "srsran/adt/bounded_bitset.h"
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#include "srsran/adt/bounded_vector.h"
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#include "srsran/phy/common/phy_common_nr.h"
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#include "srsran/phy/phch/dci.h"
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namespace srsenb {
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namespace sched_nr_impl {
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using coreset_bitmap = srsran::bounded_bitset<SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE * SRSRAN_CORESET_DURATION_MAX, true>;
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enum class pdcch_grant_type_t { sib, dl_data, ul_data };
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class slot_ue;
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struct pdcch_dl_t {
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srsran_dci_cfg_nr_t dci_cfg = {};
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srsran_dci_dl_nr_t dci = {};
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};
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static const size_t MAX_NOF_PDCCH_DL_GRANTS = 16;
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using pdcch_dl_list_t = srsran::bounded_vector<pdcch_dl_t, MAX_NOF_PDCCH_DL_GRANTS>;
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class coreset_region
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{
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public:
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coreset_region(uint32_t bwp_id_,
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uint32_t slot_idx,
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uint32_t nof_td_symbols,
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uint32_t nof_freq_resources,
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pdcch_dl_list_t& pdcch_list);
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void reset();
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/**
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* Allocates DCI space in PDCCH, avoiding in the process collisions with other users
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* @param pdcch_grant_type_t allocation type (e.g. DL data, UL data, SIB)
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* @param aggr_idx Aggregation level index (0..4)
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* @param user UE object or null in case of broadcast/RAR/paging allocation
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* @return if the allocation was successful
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*/
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bool alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, uint32_t coreset_id, slot_ue* user = nullptr);
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void rem_last_dci();
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uint32_t get_td_symbols() const { return nof_symbols; }
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uint32_t get_freq_resources() const { return nof_freq_res; }
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uint32_t nof_cces() const { return nof_freq_res * nof_symbols; }
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size_t nof_allocs() const { return dfs_tree.size(); }
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private:
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uint32_t bwp_id;
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uint32_t slot_idx;
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uint32_t nof_symbols;
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uint32_t nof_freq_res;
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// List of PDCCH grants
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struct alloc_record {
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uint32_t coreset_id;
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uint32_t aggr_idx;
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uint32_t idx;
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pdcch_grant_type_t alloc_type;
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slot_ue* ue;
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};
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srsran::bounded_vector<alloc_record, MAX_NOF_PDCCH_DL_GRANTS> dci_list;
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pdcch_dl_list_t& pdcch_dl_list;
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// DFS decision tree of PDCCH grants
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struct tree_node {
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uint16_t rnti = SRSRAN_INVALID_RNTI;
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uint32_t record_idx = 0;
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uint32_t dci_pos_idx = 0;
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srsran_dci_location_t dci_pos = {0, 0};
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/// Accumulation of all PDCCH masks for the current solution (DFS path)
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coreset_bitmap total_mask, current_mask;
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};
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using alloc_tree_dfs_t = srsran::bounded_vector<tree_node, MAX_NOF_PDCCH_DL_GRANTS>;
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alloc_tree_dfs_t dfs_tree, saved_dfs_tree;
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srsran::span<const uint32_t> get_cce_loc_table(const alloc_record& record) const;
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bool alloc_dfs_node(const alloc_record& record, uint32_t dci_idx);
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bool get_next_dfs();
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};
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} // namespace sched_nr_impl
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} // namespace srsenb
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#endif // SRSRAN_SCHED_NR_PDCCH_H
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@ -0,0 +1,93 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#ifndef SRSRAN_SCHED_LTE_COMMON_H
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#define SRSRAN_SCHED_LTE_COMMON_H
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#include "srsran/adt/bounded_bitset.h"
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#include "srsran/common/tti_point.h"
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#include "srsran/interfaces/sched_interface.h"
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namespace srsenb {
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/***********************
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* Constants
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**********************/
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constexpr float tti_duration_ms = 1;
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constexpr uint32_t NOF_AGGR_LEVEL = 4;
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/***********************
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* Helper Types
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**********************/
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/// List of CCE start positions in PDCCH
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using cce_position_list = srsran::bounded_vector<uint32_t, 6>;
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/// Map {L} -> list of CCE positions
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using cce_cfi_position_table = std::array<cce_position_list, NOF_AGGR_LEVEL>;
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/// Map {cfi, L} -> list of CCE positions
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using cce_sf_position_table = std::array<std::array<cce_position_list, NOF_AGGR_LEVEL>, SRSRAN_NOF_CFI>;
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/// Map {sf, cfi, L} -> list of CCE positions
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using cce_frame_position_table = std::array<cce_sf_position_table, SRSRAN_NOF_SF_X_FRAME>;
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/// structs to bundle together all the sched arguments, and share them with all the sched sub-components
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class sched_cell_params_t
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{
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struct regs_deleter {
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void operator()(srsran_regs_t* p);
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};
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public:
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bool set_cfg(uint32_t enb_cc_idx_,
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const sched_interface::cell_cfg_t& cfg_,
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const sched_interface::sched_args_t& sched_args);
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// convenience getters
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uint32_t nof_prbs_to_rbgs(uint32_t nof_prbs) const { return srsran::ceil_div(nof_prbs, P); }
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uint32_t nof_prb() const { return cfg.cell.nof_prb; }
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uint32_t get_dl_lb_nof_re(tti_point tti_tx_dl, uint32_t nof_prbs_alloc) const;
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uint32_t get_dl_nof_res(srsran::tti_point tti_tx_dl, const srsran_dci_dl_t& dci, uint32_t cfi) const;
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uint32_t enb_cc_idx = 0;
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sched_interface::cell_cfg_t cfg = {};
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srsran_pucch_cfg_t pucch_cfg_common = {};
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const sched_interface::sched_args_t* sched_cfg = nullptr;
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std::unique_ptr<srsran_regs_t, regs_deleter> regs;
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cce_sf_position_table common_locations = {};
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cce_frame_position_table rar_locations = {};
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std::array<uint32_t, SRSRAN_NOF_CFI> nof_cce_table = {}; ///< map cfix -> nof cces in PDCCH
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uint32_t P = 0;
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uint32_t nof_rbgs = 0;
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using dl_nof_re_table = srsran::bounded_vector<
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std::array<std::array<std::array<uint32_t, SRSRAN_NOF_CFI>, SRSRAN_NOF_SLOTS_PER_SF>, SRSRAN_NOF_SF_X_FRAME>,
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SRSRAN_MAX_PRB>;
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using dl_lb_nof_re_table = std::array<srsran::bounded_vector<uint32_t, SRSRAN_MAX_PRB>, SRSRAN_NOF_SF_X_FRAME>;
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/// Table of nof REs
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dl_nof_re_table nof_re_table;
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/// Cached computation of Lower bound of nof REs
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dl_lb_nof_re_table nof_re_lb_table;
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};
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/// Type of Allocation stored in PDSCH/PUSCH
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enum class alloc_type_t { DL_BC, DL_PCCH, DL_RAR, DL_DATA, UL_DATA };
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inline bool is_dl_ctrl_alloc(alloc_type_t a)
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{
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return a == alloc_type_t::DL_BC or a == alloc_type_t::DL_PCCH or a == alloc_type_t::DL_RAR;
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}
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} // namespace srsenb
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#endif // SRSRAN_SCHED_LTE_COMMON_H
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@ -0,0 +1,43 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#include "srsenb/hdr/stack/mac/nr/sched_nr_common.h"
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namespace srsenb {
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namespace sched_nr_impl {
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sched_cell_params::sched_cell_params(uint32_t cc_, const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_) :
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cc(cc_), cell_cfg(cell), sched_cfg(sched_cfg_)
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{}
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sched_params::sched_params(const sched_cfg_t& sched_cfg_) : sched_cfg(sched_cfg_) {}
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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void get_dci_locs(const srsran_coreset_t& coreset,
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const srsran_search_space_t& search_space,
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uint16_t rnti,
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bwp_cce_pos_list& cce_locs)
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{
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for (uint32_t sl = 0; sl < SRSRAN_NOF_SF_X_FRAME; ++sl) {
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for (uint32_t agg_idx = 0; agg_idx < MAX_NOF_AGGR_LEVELS; ++agg_idx) {
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pdcch_cce_pos_list pdcch_locs;
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cce_locs[sl][agg_idx].resize(pdcch_locs.capacity());
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uint32_t n =
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srsran_pdcch_nr_locations_coreset(&coreset, &search_space, rnti, agg_idx, sl, cce_locs[sl][agg_idx].data());
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cce_locs[sl][agg_idx].resize(n);
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}
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}
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}
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} // namespace sched_nr_impl
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} // namespace srsenb
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@ -0,0 +1,167 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#include "srsenb/hdr/stack/mac/nr/sched_nr_pdcch.h"
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#include "srsenb/hdr/stack/mac/nr/sched_nr_ue.h"
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namespace srsenb {
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namespace sched_nr_impl {
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coreset_region::coreset_region(uint32_t bwp_id_,
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uint32_t slot_idx_,
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uint32_t nof_td_symbols,
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uint32_t nof_freq_resources,
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pdcch_dl_list_t& pdcch_list_) :
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bwp_id(bwp_id_),
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slot_idx(slot_idx_),
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nof_symbols(nof_td_symbols),
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nof_freq_res(nof_freq_resources),
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pdcch_dl_list(pdcch_list_)
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{
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srsran_assert(nof_td_symbols <= SRSRAN_CORESET_DURATION_MAX,
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"Possible number of time-domain OFDM symbols in CORESET must be within {1,2,3}");
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srsran_assert(nof_freq_resources <= SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE,
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"Provided number of CORESET freq domain resources=%d is too high",
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nof_freq_resources);
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}
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void coreset_region::reset()
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{
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dfs_tree.clear();
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saved_dfs_tree.clear();
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dci_list.clear();
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pdcch_dl_list.clear();
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}
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bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, uint32_t coreset_id, slot_ue* user)
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{
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srsran_assert(aggr_idx <= 4, "Invalid DCI aggregation level=%d", 1U << aggr_idx);
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srsran_assert((user == nullptr) xor
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(alloc_type == pdcch_grant_type_t::dl_data or alloc_type == pdcch_grant_type_t::ul_data),
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"UE should be only provided for DL or UL data allocations");
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saved_dfs_tree.clear();
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alloc_record record;
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record.ue = user;
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record.aggr_idx = aggr_idx;
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record.alloc_type = alloc_type;
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record.idx = pdcch_dl_list.size();
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record.coreset_id = coreset_id;
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pdcch_dl_list.emplace_back();
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// Try to allocate grant. If it fails, attempt the same grant, but using a different permutation of past grant DCI
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// positions
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do {
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bool success = alloc_dfs_node(record, 0);
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if (success) {
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// DCI record allocation successful
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dci_list.push_back(record);
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return true;
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}
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if (dfs_tree.empty()) {
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saved_dfs_tree = dfs_tree;
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}
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} while (get_next_dfs());
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// Revert steps to initial state, before dci record allocation was attempted
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dfs_tree = saved_dfs_tree;
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pdcch_dl_list.pop_back();
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return false;
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}
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void coreset_region::rem_last_dci()
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{
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srsran_assert(not dci_list.empty(), "%s called when no PDCCH have yet been allocated", __FUNCTION__);
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// Remove DCI record
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dfs_tree.pop_back();
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dci_list.pop_back();
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pdcch_dl_list.pop_back();
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}
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bool coreset_region::get_next_dfs()
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{
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do {
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if (dfs_tree.empty()) {
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// If we reach root, the allocation failed
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return false;
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}
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// Attempt to re-add last tree node, but with a higher node child index
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uint32_t start_child_idx = dfs_tree.back().dci_pos_idx + 1;
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dfs_tree.pop_back();
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while (dfs_tree.size() < dci_list.size() and alloc_dfs_node(dci_list[dfs_tree.size()], start_child_idx)) {
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start_child_idx = 0;
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}
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} while (dfs_tree.size() < dci_list.size());
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// Finished computation of next DFS node
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return true;
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}
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bool coreset_region::alloc_dfs_node(const alloc_record& record, uint32_t start_dci_idx)
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{
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alloc_tree_dfs_t& alloc_dfs = dfs_tree;
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// Get DCI Location Table
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auto cce_locs = get_cce_loc_table(record);
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if (start_dci_idx >= cce_locs.size()) {
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return false;
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}
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tree_node node;
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node.dci_pos_idx = start_dci_idx;
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node.dci_pos.L = record.aggr_idx;
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node.rnti = record.ue != nullptr ? record.ue->rnti : SRSRAN_INVALID_RNTI;
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node.current_mask.resize(nof_cces());
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// get cumulative pdcch bitmap
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if (not alloc_dfs.empty()) {
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node.total_mask = alloc_dfs.back().total_mask;
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} else {
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node.total_mask.resize(nof_cces());
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}
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for (; node.dci_pos_idx < cce_locs.size(); ++node.dci_pos_idx) {
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node.dci_pos.ncce = cce_locs[node.dci_pos_idx];
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node.current_mask.reset();
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node.current_mask.fill(node.dci_pos.ncce, node.dci_pos.ncce + (1U << record.aggr_idx));
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if ((node.total_mask & node.current_mask).any()) {
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// there is a PDCCH collision. Try another CCE position
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continue;
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}
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// Allocation successful
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node.total_mask |= node.current_mask;
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alloc_dfs.push_back(node);
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pdcch_dl_t& pdcch_dl = pdcch_dl_list[record.idx];
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pdcch_dl.dci.ctx.location = node.dci_pos;
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return true;
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}
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return false;
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}
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srsran::span<const uint32_t> coreset_region::get_cce_loc_table(const alloc_record& record) const
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{
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switch (record.alloc_type) {
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case pdcch_grant_type_t::dl_data:
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return record.ue->cfg->cc_params[record.ue->cc]
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.bwps[bwp_id]
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.coresets[record.coreset_id]
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.cce_positions[slot_idx][record.aggr_idx];
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default:
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break;
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}
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return {};
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}
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} // namespace sched_nr_impl
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} // namespace srsenb
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