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@ -14,8 +14,10 @@
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#define SRSRAN_DUMMY_GNB_STACK_H
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#include <mutex>
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#include <srsenb/hdr/stack/mac/mac_metrics.h>
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#include <srsran/adt/circular_array.h>
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#include <srsran/common/phy_cfg_nr.h>
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#include <srsran/common/standard_streams.h>
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#include <srsran/interfaces/gnb_interfaces.h>
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class gnb_dummy_stack : public srsenb::stack_interface_phy_nr
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@ -36,6 +38,9 @@ private:
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srsran::phy_cfg_nr_t phy_cfg = {};
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bool valid = false;
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std::mutex mac_metrics_mutex;
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srsenb::mac_ue_metrics_t mac_metrics = {};
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// HARQ feedback
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class pending_ack_t
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{
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@ -61,21 +66,15 @@ private:
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srsran_pdsch_ack_nr_t get_ack()
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{
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std::unique_lock<std::mutex> lock(mutex);
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return ack;
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srsran_pdsch_ack_nr_t ret = ack;
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ack = {};
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return ret;
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}
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uint32_t get_dai()
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{
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std::unique_lock<std::mutex> lock(mutex);
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return ack.cc[0].M % 4;
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}
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void reset()
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{
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std::unique_lock<std::mutex> lock(mutex);
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ack = {};
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}
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};
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srsran::circular_array<pending_ack_t, TTIMOD_SZ> pending_ack;
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@ -264,7 +263,6 @@ public:
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logger.set_context(slot_cfg.idx);
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srsran_pdsch_ack_nr_t ack = pending_ack[slot_cfg.idx].get_ack();
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pending_ack[slot_cfg.idx].reset();
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if (ack.nof_cc > 0) {
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mac_interface_phy_nr::pucch_t pucch = {};
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@ -286,6 +284,36 @@ public:
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return 0;
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}
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int pucch_info(const srsran_slot_cfg_t& slot_cfg, const pucch_info_t& pucch_info) override
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{
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std::unique_lock<std::mutex> lock(mac_metrics_mutex);
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for (uint32_t i = 0; i < pucch_info.uci_data.cfg.ack.count; i++) {
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const srsran_harq_ack_bit_t* ack_bit = &pucch_info.uci_data.cfg.ack.bits[i];
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bool is_ok = (pucch_info.uci_data.value.ack[i] == 1) and pucch_info.uci_data.value.valid;
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uint32_t tb_count = (ack_bit->tb0 ? 1 : 0) + (ack_bit->tb1 ? 1 : 0);
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mac_metrics.tx_pkts += tb_count;
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if (not is_ok) {
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mac_metrics.tx_errors += tb_count;
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logger.debug("NACK received!");
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}
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}
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return SRSRAN_SUCCESS;
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}
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int pusch_info(const srsran_slot_cfg_t& slot_cfg, const pusch_info_t& pusch_info) override
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{
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// ... Not implemented
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return SRSRAN_ERROR;
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}
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srsenb::mac_ue_metrics_t get_metrics()
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{
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std::unique_lock<std::mutex> lock(mac_metrics_mutex);
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return mac_metrics;
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}
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};
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#endif // SRSRAN_DUMMY_GNB_STACK_H
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