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@ -228,7 +228,8 @@ int fill_pdcch_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, pdcch_cfg_
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{
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auto& cell_cfg = cfg.cell_list.at(cc);
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for (uint32_t cs_idx = 0; cs_idx < SRSRAN_UE_DL_NR_MAX_NOF_CORESET; cs_idx++) {
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// Note: Skip CORESET#0
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for (uint32_t cs_idx = 1; cs_idx < SRSRAN_UE_DL_NR_MAX_NOF_CORESET; cs_idx++) {
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if (cell_cfg.phy_cell.pdcch.coreset_present[cs_idx]) {
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auto& coreset_cfg = cell_cfg.phy_cell.pdcch.coreset[cs_idx];
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@ -263,7 +264,8 @@ int fill_pdcch_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, pdcch_cfg_
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}
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}
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for (uint32_t ss_idx = 0; ss_idx < SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE; ss_idx++) {
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// Note: Skip SearchSpace#0
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for (uint32_t ss_idx = 1; ss_idx < SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE; ss_idx++) {
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if (cell_cfg.phy_cell.pdcch.search_space_present[ss_idx]) {
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// search spaces
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auto& search_space_cfg = cell_cfg.phy_cell.pdcch.search_space[ss_idx];
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@ -309,17 +311,204 @@ int fill_pdcch_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, pdcch_cfg_
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return SRSRAN_SUCCESS;
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}
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void fill_pdsch_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, pdsch_cfg_s& out)
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{
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out.dmrs_dl_for_pdsch_map_type_a_present = true;
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out.dmrs_dl_for_pdsch_map_type_a.set_setup();
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out.dmrs_dl_for_pdsch_map_type_a.setup().dmrs_add_position_present = true;
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out.dmrs_dl_for_pdsch_map_type_a.setup().dmrs_add_position = dmrs_dl_cfg_s::dmrs_add_position_opts::pos1;
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out.tci_states_to_add_mod_list_present = true;
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out.tci_states_to_add_mod_list.resize(1);
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out.tci_states_to_add_mod_list[0].tci_state_id = 0;
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out.tci_states_to_add_mod_list[0].qcl_type1.ref_sig.set_ssb();
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out.tci_states_to_add_mod_list[0].qcl_type1.ref_sig.ssb() = 0;
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out.tci_states_to_add_mod_list[0].qcl_type1.qcl_type = asn1::rrc_nr::qcl_info_s::qcl_type_opts::type_d;
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out.res_alloc = pdsch_cfg_s::res_alloc_opts::res_alloc_type1;
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out.rbg_size = pdsch_cfg_s::rbg_size_opts::cfg1;
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out.prb_bundling_type.set_static_bundling();
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out.prb_bundling_type.static_bundling().bundle_size_present = true;
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out.prb_bundling_type.static_bundling().bundle_size =
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pdsch_cfg_s::prb_bundling_type_c_::static_bundling_s_::bundle_size_opts::wideband;
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// ZP-CSI
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out.zp_csi_rs_res_to_add_mod_list_present = false; // TEMP
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out.zp_csi_rs_res_to_add_mod_list.resize(1);
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out.zp_csi_rs_res_to_add_mod_list[0].zp_csi_rs_res_id = 0;
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.freq_domain_alloc.set_row4();
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.freq_domain_alloc.row4().from_number(0b100);
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.nrof_ports = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p4;
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.first_ofdm_symbol_in_time_domain = 8;
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.cdm_type = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::fd_cdm2;
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.density.set_one();
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.freq_band.start_rb = 0;
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out.zp_csi_rs_res_to_add_mod_list[0].res_map.freq_band.nrof_rbs = cfg.cell_list[cc].phy_cell.carrier.nof_prb;
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out.zp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset_present = true;
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out.zp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset.set_slots80() = 1;
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out.p_zp_csi_rs_res_set_present = false; // TEMP
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out.p_zp_csi_rs_res_set.set_setup();
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out.p_zp_csi_rs_res_set.setup().zp_csi_rs_res_set_id = 0;
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out.p_zp_csi_rs_res_set.setup().zp_csi_rs_res_id_list.resize(1);
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out.p_zp_csi_rs_res_set.setup().zp_csi_rs_res_id_list[0] = 0;
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}
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/// Fill InitDlBwp with gNB config
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int fill_init_dl_bwp_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, bwp_dl_ded_s& init_dl_bwp)
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{
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init_dl_bwp.pdcch_cfg_present = true;
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HANDLE_ERROR(fill_pdcch_cfg_from_enb_cfg(cfg, cc, init_dl_bwp.pdcch_cfg.set_setup()));
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init_dl_bwp.pdsch_cfg_present = true;
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fill_pdsch_cfg_from_enb_cfg(cfg, cc, init_dl_bwp.pdsch_cfg.set_setup());
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// TODO: ADD missing fields
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return SRSRAN_SUCCESS;
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}
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void fill_pucch_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, pucch_cfg_s& out)
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{
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// Make 2 PUCCH resource sets
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out.res_set_to_add_mod_list_present = true;
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out.res_set_to_add_mod_list.resize(2);
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// Make PUCCH resource set for 1-2 bit
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for (uint32_t set_id = 0; set_id < out.res_set_to_add_mod_list.size(); ++set_id) {
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auto& res_set = out.res_set_to_add_mod_list[set_id];
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res_set.pucch_res_set_id = set_id;
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res_set.res_list.resize(8);
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for (uint32_t i = 0; i < res_set.res_list.size(); ++i) {
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if (cfg.is_standalone) {
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res_set.res_list[i] = i + set_id * 8;
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} else {
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res_set.res_list[i] = set_id;
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}
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}
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}
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// Make 3 possible resources
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out.res_to_add_mod_list_present = true;
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out.res_to_add_mod_list.resize(18);
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uint32_t j = 0, j2 = 0;
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for (uint32_t i = 0; i < out.res_to_add_mod_list.size(); ++i) {
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out.res_to_add_mod_list[i].pucch_res_id = i;
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out.res_to_add_mod_list[i].intra_slot_freq_hop_present = true;
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out.res_to_add_mod_list[i].second_hop_prb_present = true;
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if (i < 8 or i == 16) {
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out.res_to_add_mod_list[i].start_prb = 51;
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out.res_to_add_mod_list[i].second_hop_prb = 0;
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out.res_to_add_mod_list[i].format.set_format1().init_cyclic_shift = (4 * (j % 3));
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out.res_to_add_mod_list[i].format.format1().nrof_symbols = 14;
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out.res_to_add_mod_list[i].format.format1().start_symbol_idx = 0;
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out.res_to_add_mod_list[i].format.format1().time_domain_occ = j / 3;
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j++;
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} else if (i < 15) {
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out.res_to_add_mod_list[i].start_prb = 1;
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out.res_to_add_mod_list[i].second_hop_prb = 50;
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out.res_to_add_mod_list[i].format.set_format2().nrof_prbs = 1;
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out.res_to_add_mod_list[i].format.format2().nrof_symbols = 2;
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out.res_to_add_mod_list[i].format.format2().start_symbol_idx = 2 * (j2 % 7);
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j2++;
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} else {
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out.res_to_add_mod_list[i].start_prb = 50;
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out.res_to_add_mod_list[i].second_hop_prb = 1;
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out.res_to_add_mod_list[i].format.set_format2().nrof_prbs = 1;
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out.res_to_add_mod_list[i].format.format2().nrof_symbols = 2;
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out.res_to_add_mod_list[i].format.format2().start_symbol_idx = 2 * (j2 % 7);
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j2++;
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}
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}
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out.format1_present = true;
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out.format1.set_setup();
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out.format2_present = true;
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out.format2.set_setup();
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out.format2.setup().max_code_rate_present = true;
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out.format2.setup().max_code_rate = pucch_max_code_rate_opts::zero_dot25;
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// SR resources
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out.sched_request_res_to_add_mod_list_present = true;
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out.sched_request_res_to_add_mod_list.resize(1);
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auto& sr_res1 = out.sched_request_res_to_add_mod_list[0];
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sr_res1.sched_request_res_id = 1;
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sr_res1.sched_request_id = 0;
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sr_res1.periodicity_and_offset_present = true;
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sr_res1.periodicity_and_offset.set_sl40() = 0;
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sr_res1.res_present = true;
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sr_res1.res = 16;
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// DL data
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out.dl_data_to_ul_ack_present = true;
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if (cfg.cell_list[cc].duplex_mode == SRSRAN_DUPLEX_MODE_FDD) {
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out.dl_data_to_ul_ack.resize(1);
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out.dl_data_to_ul_ack[0] = 4;
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} else {
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out.dl_data_to_ul_ack.resize(6);
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out.dl_data_to_ul_ack[0] = 6;
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out.dl_data_to_ul_ack[1] = 5;
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out.dl_data_to_ul_ack[2] = 4;
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out.dl_data_to_ul_ack[3] = 4;
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out.dl_data_to_ul_ack[4] = 4;
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out.dl_data_to_ul_ack[5] = 4;
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}
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}
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void fill_pusch_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, pusch_cfg_s& out)
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{
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out.dmrs_ul_for_pusch_map_type_a_present = true;
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out.dmrs_ul_for_pusch_map_type_a.set_setup();
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out.dmrs_ul_for_pusch_map_type_a.setup().dmrs_add_position_present = true;
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out.dmrs_ul_for_pusch_map_type_a.setup().dmrs_add_position = dmrs_ul_cfg_s::dmrs_add_position_opts::pos1;
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// PUSH power control skipped
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out.res_alloc = pusch_cfg_s::res_alloc_opts::res_alloc_type1;
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// UCI
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out.uci_on_pusch_present = true;
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out.uci_on_pusch.set_setup();
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out.uci_on_pusch.setup().beta_offsets_present = true;
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out.uci_on_pusch.setup().beta_offsets.set_semi_static();
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auto& beta_offset_semi_static = out.uci_on_pusch.setup().beta_offsets.semi_static();
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beta_offset_semi_static.beta_offset_ack_idx1_present = true;
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beta_offset_semi_static.beta_offset_ack_idx1 = 9;
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beta_offset_semi_static.beta_offset_ack_idx2_present = true;
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beta_offset_semi_static.beta_offset_ack_idx2 = 9;
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beta_offset_semi_static.beta_offset_ack_idx3_present = true;
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beta_offset_semi_static.beta_offset_ack_idx3 = 9;
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beta_offset_semi_static.beta_offset_csi_part1_idx1_present = true;
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beta_offset_semi_static.beta_offset_csi_part1_idx1 = 6;
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beta_offset_semi_static.beta_offset_csi_part1_idx2_present = true;
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beta_offset_semi_static.beta_offset_csi_part1_idx2 = 6;
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beta_offset_semi_static.beta_offset_csi_part2_idx1_present = true;
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beta_offset_semi_static.beta_offset_csi_part2_idx1 = 6;
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beta_offset_semi_static.beta_offset_csi_part2_idx2_present = true;
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beta_offset_semi_static.beta_offset_csi_part2_idx2 = 6;
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out.uci_on_pusch.setup().scaling = uci_on_pusch_s::scaling_opts::f1;
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}
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void fill_init_ul_bwp_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, bwp_ul_ded_s& out)
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{
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if (cfg.is_standalone) {
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out.pucch_cfg_present = true;
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fill_pucch_cfg_from_enb_cfg(cfg, cc, out.pucch_cfg.set_setup());
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out.pusch_cfg_present = true;
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fill_pusch_cfg_from_enb_cfg(cfg, cc, out.pusch_cfg.set_setup());
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}
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}
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/// Fill InitUlBwp with gNB config
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void fill_ul_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, ul_cfg_s& out)
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{
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out.init_ul_bwp_present = true;
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fill_init_ul_bwp_from_enb_cfg(cfg, cc, out.init_ul_bwp);
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}
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/// Fill ServingCellConfig with gNB config
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int fill_serv_cell_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, serving_cell_cfg_s& serv_cell)
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{
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@ -329,6 +518,16 @@ int fill_serv_cell_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, serving_ce
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serv_cell.init_dl_bwp_present = true;
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fill_init_dl_bwp_from_enb_cfg(cfg, cc, serv_cell.init_dl_bwp);
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serv_cell.first_active_dl_bwp_id_present = true;
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if (cfg.cell_list[0].duplex_mode == SRSRAN_DUPLEX_MODE_FDD) {
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serv_cell.first_active_dl_bwp_id = 0;
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} else {
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serv_cell.first_active_dl_bwp_id = 1;
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}
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serv_cell.ul_cfg_present = true;
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fill_ul_cfg_from_enb_cfg(cfg, cc, serv_cell.ul_cfg);
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// TODO: remaining fields
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return SRSRAN_SUCCESS;
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@ -584,6 +783,95 @@ int fill_sp_cell_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, sp_cell_
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return SRSRAN_SUCCESS;
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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void fill_srb1(const rrc_nr_cfg_t& cfg, rlc_bearer_cfg_s& srb1)
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{
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srb1.lc_ch_id = 1;
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srb1.served_radio_bearer_present = true;
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srb1.served_radio_bearer.set_srb_id() = 1;
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srb1.rlc_cfg_present = true;
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ul_am_rlc_s& am_ul = srb1.rlc_cfg.set_am().ul_am_rlc;
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am_ul.sn_field_len_present = true;
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am_ul.sn_field_len.value = asn1::rrc_nr::sn_field_len_am_opts::size12;
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am_ul.t_poll_retx.value = asn1::rrc_nr::t_poll_retx_opts::ms45;
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am_ul.poll_pdu.value = asn1::rrc_nr::poll_pdu_opts::infinity;
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am_ul.poll_byte.value = asn1::rrc_nr::poll_byte_opts::infinity;
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am_ul.max_retx_thres.value = asn1::rrc_nr::ul_am_rlc_s::max_retx_thres_opts::t8;
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dl_am_rlc_s& am_dl = srb1.rlc_cfg.am().dl_am_rlc;
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am_dl.sn_field_len_present = true;
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am_dl.sn_field_len.value = asn1::rrc_nr::sn_field_len_am_opts::size12;
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am_dl.t_reassembly.value = t_reassembly_opts::ms35;
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am_dl.t_status_prohibit.value = asn1::rrc_nr::t_status_prohibit_opts::ms0;
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// mac-LogicalChannelConfig -- Cond LCH-Setup
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srb1.mac_lc_ch_cfg_present = true;
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srb1.mac_lc_ch_cfg.ul_specific_params_present = true;
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srb1.mac_lc_ch_cfg.ul_specific_params.prio = 1;
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srb1.mac_lc_ch_cfg.ul_specific_params.prioritised_bit_rate.value =
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lc_ch_cfg_s::ul_specific_params_s_::prioritised_bit_rate_opts::infinity;
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srb1.mac_lc_ch_cfg.ul_specific_params.bucket_size_dur.value =
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lc_ch_cfg_s::ul_specific_params_s_::bucket_size_dur_opts::ms5;
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srb1.mac_lc_ch_cfg.ul_specific_params.lc_ch_group_present = true;
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srb1.mac_lc_ch_cfg.ul_specific_params.lc_ch_group = 0;
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srb1.mac_lc_ch_cfg.ul_specific_params.sched_request_id_present = true;
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srb1.mac_lc_ch_cfg.ul_specific_params.sched_request_id = 0;
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srb1.mac_lc_ch_cfg.ul_specific_params.lc_ch_sr_mask = false;
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srb1.mac_lc_ch_cfg.ul_specific_params.lc_ch_sr_delay_timer_applied = false;
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}
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/// Fill MasterCellConfig with gNB config
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int fill_master_cell_cfg_from_enb_cfg(const rrc_nr_cfg_t& cfg, uint32_t cc, asn1::rrc_nr::cell_group_cfg_s& out)
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{
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out.cell_group_id = 0;
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out.rlc_bearer_to_add_mod_list_present = true;
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out.rlc_bearer_to_add_mod_list.resize(1);
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fill_srb1(cfg, out.rlc_bearer_to_add_mod_list[0]);
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// mac-CellGroupConfig -- Need M
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out.mac_cell_group_cfg_present = true;
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out.mac_cell_group_cfg.sched_request_cfg_present = true;
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out.mac_cell_group_cfg.sched_request_cfg.sched_request_to_add_mod_list_present = true;
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out.mac_cell_group_cfg.sched_request_cfg.sched_request_to_add_mod_list.resize(1);
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out.mac_cell_group_cfg.sched_request_cfg.sched_request_to_add_mod_list[0].sched_request_id = 0;
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out.mac_cell_group_cfg.sched_request_cfg.sched_request_to_add_mod_list[0].sr_trans_max.value =
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sched_request_to_add_mod_s::sr_trans_max_opts::n64;
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out.mac_cell_group_cfg.bsr_cfg_present = true;
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out.mac_cell_group_cfg.bsr_cfg.periodic_bsr_timer.value = bsr_cfg_s::periodic_bsr_timer_opts::sf20;
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out.mac_cell_group_cfg.bsr_cfg.retx_bsr_timer.value = bsr_cfg_s::retx_bsr_timer_opts::sf320;
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out.mac_cell_group_cfg.tag_cfg_present = true;
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out.mac_cell_group_cfg.tag_cfg.tag_to_add_mod_list_present = true;
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out.mac_cell_group_cfg.tag_cfg.tag_to_add_mod_list.resize(1);
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out.mac_cell_group_cfg.tag_cfg.tag_to_add_mod_list[0].tag_id = 0;
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out.mac_cell_group_cfg.tag_cfg.tag_to_add_mod_list[0].time_align_timer.value = time_align_timer_opts::infinity;
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out.mac_cell_group_cfg.phr_cfg_present = true;
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|
|
phr_cfg_s& phr = out.mac_cell_group_cfg.phr_cfg.set_setup();
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phr.phr_periodic_timer.value = asn1::rrc_nr::phr_cfg_s::phr_periodic_timer_opts::sf500;
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phr.phr_prohibit_timer.value = asn1::rrc_nr::phr_cfg_s::phr_prohibit_timer_opts::sf200;
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phr.phr_tx_pwr_factor_change.value = asn1::rrc_nr::phr_cfg_s::phr_tx_pwr_factor_change_opts::db3;
|
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|
|
phr.multiple_phr = false;
|
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|
|
phr.dummy = false;
|
|
|
|
|
phr.phr_type2_other_cell = false;
|
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|
|
|
phr.phr_mode_other_cg.value = asn1::rrc_nr::phr_cfg_s::phr_mode_other_cg_opts::real;
|
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|
out.mac_cell_group_cfg.skip_ul_tx_dynamic = false;
|
|
|
|
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|
|
|
|
// physicalCellGroupConfig -- Need M
|
|
|
|
|
out.phys_cell_group_cfg_present = true;
|
|
|
|
|
out.phys_cell_group_cfg.p_nr_fr1_present = true;
|
|
|
|
|
out.phys_cell_group_cfg.p_nr_fr1 = 10;
|
|
|
|
|
out.phys_cell_group_cfg.pdsch_harq_ack_codebook.value =
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|
|
|
phys_cell_group_cfg_s::pdsch_harq_ack_codebook_opts::dynamic_value;
|
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|
|
|
|
|
|
|
|
// spCellConfig -- Need M
|
|
|
|
|
out.sp_cell_cfg_present = true;
|
|
|
|
|
fill_sp_cell_cfg_from_enb_cfg(cfg, cc, out.sp_cell_cfg);
|
|
|
|
|
out.sp_cell_cfg.recfg_with_sync_present = false;
|
|
|
|
|
|
|
|
|
|
return SRSRAN_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
|
|
int fill_mib_from_enb_cfg(const rrc_nr_cfg_t& cfg, asn1::rrc_nr::mib_s& mib)
|
|
|
|
|
{
|
|
|
|
|
uint32_t scs =
|
|
|
|
|