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@ -576,6 +576,7 @@ sched::sched() : bc_aggr_level(0), rar_aggr_level(0), P(0), si_n_rbg(0), rar_n_r
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bzero(&sched_cfg, sizeof(sched_cfg));
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bzero(&common_locations, sizeof(common_locations));
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bzero(&pdsch_re, sizeof(pdsch_re));
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tti_dl_mask.resize(10, 1);
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for (int i = 0; i < 3; i++) {
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bzero(rar_locations[i], sizeof(sched_ue::sched_dci_cce_t) * 10);
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@ -1006,6 +1007,11 @@ int sched::ul_sr_info(uint32_t tti, uint16_t rnti)
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return ret;
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}
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void sched::set_dl_tti_mask(uint8_t* tti_mask, uint32_t nof_sfs)
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{
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tti_dl_mask.assign(tti_mask, tti_mask + nof_sfs);
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}
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void sched::tpc_inc(uint16_t rnti)
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{
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pthread_rwlock_rdlock(&rwlock);
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@ -1051,7 +1057,9 @@ sched::tti_sched_t* sched::new_tti(uint32_t tti_rx)
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generate_phich(tti_sched);
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/* Schedule DL */
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generate_dl_sched(tti_sched);
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if (tti_dl_mask[tti_rx % tti_dl_mask.size()] > 0) {
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generate_dl_sched(tti_sched);
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}
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/* Schedule UL */
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generate_ul_sched(tti_sched);
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