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@ -12,16 +12,16 @@
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#include "srslte/phy/phch/ra_dl_nr.h"
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#include "srslte/phy/utils/debug.h"
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static void sliv_to_s_and_l(uint32_t sliv, uint32_t* S, uint32_t* L)
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static void compute_s_and_l(uint32_t N, uint32_t v, uint32_t* S, uint32_t* L)
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{
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// S values can be 0 to 3
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uint32_t low = sliv % 14;
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if (low < 7) {
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uint32_t low = v % N;
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uint32_t high = v / N;
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if (high + 1 + low <= N) {
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*S = low;
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*L = sliv / 14 + 1;
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*L = high + 1;
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} else {
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*S = 14 - 1 - low;
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*L = 14 - sliv / 14 + 1;
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*S = N - 1 - low;
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*L = N - high + 1;
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}
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}
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@ -128,14 +128,16 @@ int srslte_ra_dl_nr_time_default_A(uint32_t m, srslte_dmrs_sch_typeA_pos_t dmrs_
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void srslte_ra_dl_nr_time_hl(const srslte_pdsch_time_ra_t* hl_ra_cfg, srslte_sch_grant_nr_t* grant)
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{
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// Compute S and L from SLIV from higher layers
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sliv_to_s_and_l(hl_ra_cfg->sliv, &grant->S, &grant->L);
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compute_s_and_l(SRSLTE_NSYMB_PER_SLOT_NR, hl_ra_cfg->sliv, &grant->S, &grant->L);
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grant->k0 = hl_ra_cfg->k0;
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grant->mapping = hl_ra_cfg->mapping_type;
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}
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int srslte_ra_dl_nr_time(const srslte_sch_cfg_nr_t* cfg,
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int srslte_ra_dl_nr_time(const srslte_pdsch_cfg_nr_t* cfg,
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const srslte_rnti_type_t rnti_type,
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const srslte_search_space_type_t ss_type,
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const uint32_t coreset_id,
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const uint8_t m,
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srslte_sch_grant_nr_t* grant)
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{
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@ -149,40 +151,72 @@ int srslte_ra_dl_nr_time(const srslte_sch_cfg_nr_t* cfg,
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return SRSLTE_ERROR_INVALID_INPUTS;
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}
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// Determine which PDSCH Time domain RA configuration to apply (Table 5.1.2.1.1-1)
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if (cfg->pdsch_time_is_default) {
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// Note: Only Default A is supported, which corresponds SS/PBCH block and coreset mux pattern 1
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srslte_ra_dl_nr_time_default_A(m, cfg->dmrs_typeA.typeA_pos, grant);
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// Determine which PDSCH Time domain RA configuration to apply (TS 38.214 Table 5.1.2.1.1-1)
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if (rnti_type == srslte_rnti_type_si && ss_type == srslte_search_space_type_common_0) {
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// Row 1
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ERROR("Row not implemented");
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} else if (rnti_type == srslte_rnti_type_si && ss_type == srslte_search_space_type_common_0A) {
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// Row 2
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ERROR("Row not implemented");
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} else if ((rnti_type == srslte_rnti_type_ra || rnti_type == srslte_rnti_type_tc) &&
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ss_type == srslte_search_space_type_common_1) {
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// Row 3
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if (cfg->nof_common_pdsch_time_ra > 0) {
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srslte_ra_dl_nr_time_hl(&cfg->common_pdsch_time_ra[m], grant);
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} else {
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// Note: Only Default A is supported, which corresponds SS/PBCH block and coreset mux pattern 1
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srslte_ra_dl_nr_time_default_A(m, cfg->typeA_pos, grant);
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}
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} else if (rnti_type == srslte_rnti_type_p && ss_type == srslte_search_space_type_common_2) {
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// Row 4
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ERROR("Row not implemented");
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} else if ((rnti_type == srslte_rnti_type_c || rnti_type == srslte_rnti_type_mcs_c ||
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rnti_type == srslte_rnti_type_cs) &&
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SRSLTE_SEARCH_SPACE_IS_COMMON(ss_type) && coreset_id == 0) {
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// Row 5
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if (cfg->nof_common_pdsch_time_ra > 0) {
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srslte_ra_dl_nr_time_hl(&cfg->common_pdsch_time_ra[m], grant);
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} else {
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srslte_ra_dl_nr_time_default_A(m, cfg->typeA_pos, grant);
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}
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} else if ((rnti_type == srslte_rnti_type_c || rnti_type == srslte_rnti_type_mcs_c ||
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rnti_type == srslte_rnti_type_cs) &&
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((SRSLTE_SEARCH_SPACE_IS_COMMON(ss_type) && coreset_id != 0) || ss_type == srslte_search_space_type_ue)) {
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// Row 6
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if (cfg->nof_pdsch_time_ra > 0) {
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srslte_ra_dl_nr_time_hl(&cfg->pdsch_time_ra[m], grant);
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} else if (cfg->nof_common_pdsch_time_ra > 0) {
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srslte_ra_dl_nr_time_hl(&cfg->common_pdsch_time_ra[m], grant);
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} else {
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srslte_ra_dl_nr_time_default_A(m, cfg->typeA_pos, grant);
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}
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} else {
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srslte_ra_dl_nr_time_hl(&cfg->pdsch_time_ra[m], grant);
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ERROR("Unhandled case");
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}
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// Validate S and L parameters
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if (!srslte_ra_dl_nr_time_validate(grant)) {
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ERROR("Invalid Time RA\n");
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ERROR("Invalid Time RA S=%d; L=%d; m=%d\n", grant->S, grant->L, m);
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return SRSLTE_ERROR;
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}
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return SRSLTE_SUCCESS;
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}
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int srslte_ra_dl_nr_nof_dmrs_cdm_groups_without_data_format_1_0(const srslte_sch_cfg_nr_t* pdsch_cfg,
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srslte_sch_grant_nr_t* grant)
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int srslte_ra_dl_nr_nof_dmrs_cdm_groups_without_data_format_1_0(const srslte_dmrs_sch_cfg_t* cfg,
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srslte_sch_grant_nr_t* grant)
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{
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if (pdsch_cfg == NULL || grant == NULL) {
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if (cfg == NULL || grant == NULL) {
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return SRSLTE_ERROR_INVALID_INPUTS;
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}
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const srslte_dmrs_sch_cfg_t* dmrs_cfg =
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grant->mapping == srslte_sch_mapping_type_A ? &pdsch_cfg->dmrs_typeA : &pdsch_cfg->dmrs_typeB;
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/* According to TS 38.214 V15.10.0 5.1.6.1.3 CSI-RS for mobility:
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* When receiving PDSCH scheduled by DCI format 1_0, the UE shall assume the number of DM-RS CDM groups without data
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* is 1 which corresponds to CDM group 0 for the case of PDSCH with allocation duration of 2 symbols, and the UE shall
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* assume that the number of DM-RS CDM groups without data is 2 which corresponds to CDM group {0,1} for all other
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* cases.
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* is 1 which corresponds to CDM group 0 for the case of PDSCH with allocation duration of 2 symbols, and the UE
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* shall assume that the number of DM-RS CDM groups without data is 2 which corresponds to CDM group {0,1} for all
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* other cases.
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*/
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if (dmrs_cfg->length == srslte_dmrs_sch_len_2) {
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if (cfg->length == srslte_dmrs_sch_len_2) {
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grant->nof_dmrs_cdm_groups_without_data = 1;
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} else {
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grant->nof_dmrs_cdm_groups_without_data = 2;
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@ -205,10 +239,10 @@ uint32_t srslte_ra_dl_nr_type0_P(uint32_t bwp_size, bool config_is_1)
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}
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}
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static int ra_freq_type0(const srslte_carrier_nr_t* carrier,
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const srslte_sch_cfg_nr_t* cfg,
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const srslte_dci_dl_nr_t* dci_dl,
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srslte_sch_grant_nr_t* grant)
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static int ra_freq_type0(const srslte_carrier_nr_t* carrier,
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const srslte_pdsch_cfg_nr_t* cfg,
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const srslte_dci_dl_nr_t* dci_dl,
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srslte_sch_grant_nr_t* grant)
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{
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uint32_t P = srslte_ra_dl_nr_type0_P(carrier->nof_prb, cfg->rbg_size_cfg_1);
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@ -234,10 +268,42 @@ static int ra_freq_type0(const srslte_carrier_nr_t* carrier,
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return 0;
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}
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int srslte_ra_dl_nr_freq(const srslte_carrier_nr_t* carrier,
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const srslte_sch_cfg_nr_t* cfg,
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const srslte_dci_dl_nr_t* dci_dl,
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srslte_sch_grant_nr_t* grant)
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static int
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ra_freq_type1(const srslte_carrier_nr_t* carrier, const srslte_dci_dl_nr_t* dci_dl, srslte_sch_grant_nr_t* grant)
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{
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uint32_t riv = dci_dl->freq_domain_assigment;
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uint32_t N_bwp_size = carrier->nof_prb;
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uint32_t start = 0;
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uint32_t len = 0;
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compute_s_and_l(N_bwp_size, riv, &start, &len);
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if (start + len > N_bwp_size) {
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ERROR("RIV 0x%x for BWP size %d resulted in freq=%d:%d\n", riv, N_bwp_size, start, len);
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return SRSLTE_ERROR;
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}
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for (uint32_t i = 0; i < start; i++) {
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grant->prb_idx[i] = false;
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}
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for (uint32_t i = start; i < start + len; i++) {
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grant->prb_idx[i] = true;
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}
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for (uint32_t i = start + len; i < SRSLTE_MAX_PRB_NR; i++) {
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grant->prb_idx[i] = false;
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}
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grant->nof_prb = len;
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return SRSLTE_SUCCESS;
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}
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int srslte_ra_dl_nr_freq(const srslte_carrier_nr_t* carrier,
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const srslte_pdsch_cfg_nr_t* cfg,
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const srslte_dci_dl_nr_t* dci_dl,
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srslte_sch_grant_nr_t* grant)
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{
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if (cfg == NULL || grant == NULL || dci_dl == NULL) {
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@ -246,11 +312,11 @@ int srslte_ra_dl_nr_freq(const srslte_carrier_nr_t* carrier,
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// RA scheme
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if (dci_dl->format == srslte_dci_format_nr_1_0) {
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ra_freq_type0(carrier, cfg, dci_dl, grant);
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} else {
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ERROR("Only DCI Format 1_0 is supported\n");
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return SRSLTE_ERROR;
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// when the scheduling grant is received with DCI format 1_0 , then downlink resource allocation type 1 is used.
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return ra_freq_type1(carrier, dci_dl, grant);
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}
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return SRSLTE_SUCCESS;
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ra_freq_type0(carrier, cfg, dci_dl, grant);
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ERROR("Only DCI Format 1_0 is supported\n");
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return SRSLTE_ERROR;
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}
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Xavier Arteaga
4 years ago
committed by
Xavier Arteaga