From 102cb196e1dfc3ed4820a4c758da535f29bff562 Mon Sep 17 00:00:00 2001 From: Francisco Date: Fri, 19 Feb 2021 16:59:42 +0000 Subject: [PATCH] Addition of enb cfg option to choose between PUCCH with multiplexing and without. Change default prach offset to 4. - The new prach offset of 4 accounts for the size of the PUCCH-ACK region with 100 prbs --- lib/include/srslte/interfaces/sched_interface.h | 3 ++- srsenb/sib.conf.example | 2 +- srsenb/src/main.cc | 2 ++ srsenb/src/stack/mac/sched_grid.cc | 5 ++++- .../src/stack/mac/sched_phy_ch/sf_cch_allocator.cc | 3 +-- srsenb/test/mac/sched_common_test_suite.cc | 12 +++++++----- srsenb/test/mac/sched_test_utils.h | 2 +- 7 files changed, 18 insertions(+), 11 deletions(-) diff --git a/lib/include/srslte/interfaces/sched_interface.h b/lib/include/srslte/interfaces/sched_interface.h index bc0939117..76a699169 100644 --- a/lib/include/srslte/interfaces/sched_interface.h +++ b/lib/include/srslte/interfaces/sched_interface.h @@ -54,10 +54,10 @@ public: uint32_t min_nof_ctrl_symbols = 1; uint32_t max_nof_ctrl_symbols = 3; int max_aggr_level = 3; + bool pucch_mux_enabled = false; }; struct cell_cfg_t { - // Main cell configuration (used to calculate DCI locations in scheduler) srslte_cell_t cell; @@ -81,6 +81,7 @@ public: uint32_t maxharq_msg3tx; uint32_t n1pucch_an; uint32_t delta_pucch_shift; + bool pucch_mux_enabled = false; // If non-negative, statically allocate N prbs at the edges of the uplink for PUCCH int nrb_pucch; diff --git a/srsenb/sib.conf.example b/srsenb/sib.conf.example index 52f5a348a..0084a3f11 100644 --- a/srsenb/sib.conf.example +++ b/srsenb/sib.conf.example @@ -47,7 +47,7 @@ sib2 = { high_speed_flag = false; prach_config_index = 3; - prach_freq_offset = 2; + prach_freq_offset = 4; zero_correlation_zone_config = 5; }; }; diff --git a/srsenb/src/main.cc b/srsenb/src/main.cc index 92da8e75b..2a84d5453 100644 --- a/srsenb/src/main.cc +++ b/srsenb/src/main.cc @@ -147,6 +147,8 @@ void parse_args(all_args_t* args, int argc, char* argv[]) ("scheduler.max_aggr_level", bpo::value(&args->stack.mac.sched.max_aggr_level)->default_value(-1), "Optional maximum aggregation level index (l=log2(L)) ") ("scheduler.max_nof_ctrl_symbols", bpo::value(&args->stack.mac.sched.max_nof_ctrl_symbols)->default_value(3), "Number of control symbols") ("scheduler.min_nof_ctrl_symbols", bpo::value(&args->stack.mac.sched.min_nof_ctrl_symbols)->default_value(1), "Minimum number of control symbols") + ("scheduler.pucch_multiplex_enable", bpo::value(&args->stack.mac.sched.pucch_mux_enabled)->default_value(false), "Enable PUCCH multiplexing") + /* Downlink Channel emulator section */ ("channel.dl.enable", bpo::value(&args->phy.dl_channel_args.enable)->default_value(false), "Enable/Disable internal Downlink channel emulator") diff --git a/srsenb/src/stack/mac/sched_grid.cc b/srsenb/src/stack/mac/sched_grid.cc index 432c5cea7..a5d9858b6 100644 --- a/srsenb/src/stack/mac/sched_grid.cc +++ b/srsenb/src/stack/mac/sched_grid.cc @@ -134,7 +134,10 @@ void sf_grid_t::init(const sched_cell_params_t& cell_params_) // Compute reserved PRBs for CQI, SR and HARQ-ACK, and store it in a bitmask pucch_mask.resize(cc_cfg->nof_prb()); - pucch_nrb = (cc_cfg->cfg.nrb_pucch > 0) ? (uint32_t)cc_cfg->cfg.nrb_pucch : 0; + pucch_nrb = (cc_cfg->cfg.nrb_pucch > 0) ? (uint32_t)cc_cfg->cfg.nrb_pucch : 0; + srslte_pucch_cfg_t pucch_cfg = cell_params_.pucch_cfg_common; + pucch_cfg.n_pucch = cc_cfg->nof_cce_table[SRSLTE_NOF_CFI - 1] - 1 + cc_cfg->cfg.n1pucch_an; + pucch_nrb = std::max(pucch_nrb, srslte_pucch_m(&pucch_cfg, cc_cfg->cfg.cell.cp) / 2 + 1); if (pucch_nrb > 0) { pucch_mask.fill(0, pucch_nrb); pucch_mask.fill(cc_cfg->nof_prb() - pucch_nrb, cc_cfg->nof_prb()); diff --git a/srsenb/src/stack/mac/sched_phy_ch/sf_cch_allocator.cc b/srsenb/src/stack/mac/sched_phy_ch/sf_cch_allocator.cc index 3a76fe65e..f4d28b730 100644 --- a/srsenb/src/stack/mac/sched_phy_ch/sf_cch_allocator.cc +++ b/srsenb/src/stack/mac/sched_phy_ch/sf_cch_allocator.cc @@ -217,8 +217,7 @@ bool sf_cch_allocator::alloc_tree_t::add_tree_node_leaves(int } pucch_prbidx = srslte_pucch_n_prb(&cc_cfg->cfg.cell, pucch_cfg, 0); - bool test = pucch_prbidx != 1 and pucch_prbidx != (uint8_t)(cc_cfg->nof_prb() - 2); - if (parent_pucch_mask.test(pucch_prbidx)) { + if (not cc_cfg->cfg.pucch_mux_enabled and parent_pucch_mask.test(pucch_prbidx)) { // PUCCH allocation would collide with other PUCCH/PUSCH grants. Try another CCE position continue; } diff --git a/srsenb/test/mac/sched_common_test_suite.cc b/srsenb/test/mac/sched_common_test_suite.cc index cc141d0ce..288b2e5b8 100644 --- a/srsenb/test/mac/sched_common_test_suite.cc +++ b/srsenb/test/mac/sched_common_test_suite.cc @@ -46,11 +46,13 @@ int test_pusch_collisions(const sf_output_res_t& sf_out, uint32_t enb_cc_idx, co } /* TEST: check collisions in PUCCH */ - bool strict = nof_prb != 6 or (not is_prach_tti_tx_ul); // and not tti_data.ul_pending_msg3_present); - try_ul_fill({0, (uint32_t)cell_params.cfg.nrb_pucch}, "PUCCH", strict); - try_ul_fill({cell_params.cfg.cell.nof_prb - cell_params.cfg.nrb_pucch, (uint32_t)cell_params.cfg.cell.nof_prb}, - "PUCCH", - strict); + bool strict = nof_prb != 6 or (not is_prach_tti_tx_ul); // and not tti_data.ul_pending_msg3_present); + uint32_t pucch_nrb = (cell_params.cfg.nrb_pucch > 0) ? (uint32_t)cell_params.cfg.nrb_pucch : 0; + srslte_pucch_cfg_t pucch_cfg = cell_params.pucch_cfg_common; + pucch_cfg.n_pucch = cell_params.nof_cce_table[SRSLTE_NOF_CFI - 1] - 1 + cell_params.cfg.n1pucch_an; + pucch_nrb = std::max(pucch_nrb, srslte_pucch_m(&pucch_cfg, cell_params.cfg.cell.cp) / 2 + 1); + try_ul_fill({0, pucch_nrb}, "PUCCH", strict); + try_ul_fill({cell_params.cfg.cell.nof_prb - pucch_nrb, (uint32_t)cell_params.cfg.cell.nof_prb}, "PUCCH", strict); /* TEST: check collisions in the UL PUSCH */ for (uint32_t i = 0; i < ul_result.nof_dci_elems; ++i) { diff --git a/srsenb/test/mac/sched_test_utils.h b/srsenb/test/mac/sched_test_utils.h index fc561f37a..7a3a83645 100644 --- a/srsenb/test/mac/sched_test_utils.h +++ b/srsenb/test/mac/sched_test_utils.h @@ -44,7 +44,7 @@ inline srsenb::sched_interface::cell_cfg_t generate_default_cell_cfg(uint32_t no cell_cfg.sibs[1].period_rf = 16; cell_cfg.si_window_ms = 40; cell_cfg.nrb_pucch = (cell_cfg_phy.nof_prb == 6) ? 1 : 2; - cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 2; + cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 4; cell_cfg.prach_rar_window = 3; cell_cfg.maxharq_msg3tx = 3; cell_cfg.initial_dl_cqi = 6;