5g-team
/
srsRAN_4G
mirror of https://github.com/pvnis/srsRAN_4G.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

disable PHR handling in the UL sched by default

Browse Source
master
Francisco Paisana 4 years ago
parent e27c0869e5
commit 099dad8cb1
8 changed files with 25 additions and 16 deletions
Show Stats Download Patch File Download Diff File

1
lib/include/srslte/interfaces/enb_rrc_interface_types.h
Unescape Escape View File

@ -55,6 +55,7 @@ struct cell_cfg_t {
double ul_freq_hz;
int target_ul_sinr_db;
uint32_t initial_dl_cqi;
bool enable_phr_handling;
std::vector<scell_cfg_t> scell_list;
rrc_meas_cfg_t meas_cfg;
};

3
lib/include/srslte/interfaces/sched_interface.h
Unescape Escape View File

@ -67,6 +67,8 @@ public:
/* pusch configuration */
srslte_pusch_hopping_cfg_t pusch_hopping_cfg;
float target_ul_sinr;
bool enable_phr_handling;
bool enable_64qam;
/* prach configuration */
uint32_t prach_config;
@ -78,7 +80,6 @@ public:
uint32_t maxharq_msg3tx;
uint32_t n1pucch_an;
uint32_t delta_pucch_shift;
bool enable_64qam;
// If non-negative, statically allocate N prbs at the edges of the uplink for PUCCH
int nrb_pucch;

18
srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h
Unescape Escape View File

@ -33,12 +33,13 @@ class tpc
public:
static constexpr int PHR_NEG_NOF_PRB = 1;
tpc(uint32_t cell_nof_prb, float target_snr_dB_ = -1.0) :
tpc(uint32_t cell_nof_prb, float target_snr_dB_ = -1.0, bool phr_handling_flag_ = false) :
nof_prb(cell_nof_prb),
target_snr_dB(target_snr_dB_),
snr_avg(0.1, target_snr_dB_),
win_pusch_tpc_values(FDD_HARQ_DELAY_UL_MS + FDD_HARQ_DELAY_DL_MS),
win_pucch_tpc_values(FDD_HARQ_DELAY_DL_MS + FDD_HARQ_DELAY_UL_MS)
win_pucch_tpc_values(FDD_HARQ_DELAY_DL_MS + FDD_HARQ_DELAY_UL_MS),
phr_handling_flag(phr_handling_flag_)
{
max_prbs_cached = nof_prb;
}
@ -52,11 +53,13 @@ public:
pusch_phr_flag = false;
// compute and cache the max nof UL PRBs that avoids overflowing PHR
max_prbs_cached = PHR_NEG_NOF_PRB;
for (int n = nof_prb; n > PHR_NEG_NOF_PRB; --n) {
if (last_phr >= 10 * log10(n)) {
max_prbs_cached = n;
break;
if (phr_handling_flag) {
max_prbs_cached = PHR_NEG_NOF_PRB;
for (int n = nof_prb; n > PHR_NEG_NOF_PRB; --n) {
if (last_phr >= 10 * log10(n)) {
max_prbs_cached = n;
break;
}
}
}
}
@ -178,6 +181,7 @@ private:
uint32_t nof_prb;
float target_snr_dB;
bool phr_handling_flag;
// PHR-related variables
int last_phr = undefined_phr;

1
srsenb/src/enb_cfg_parser.cc
Unescape Escape View File

@ -735,6 +735,7 @@ static int parse_cell_list(all_args_t* args, rrc_cfg_t* rrc_cfg, Setting& root)
parse_default_field(cell_cfg.initial_dl_cqi, cellroot, "initial_dl_cqi", 5u);
parse_default_field(cell_cfg.meas_cfg.meas_gap_period, cellroot, "meas_gap_period", 0u);
HANDLEPARSERCODE(parse_default_field(cell_cfg.target_ul_sinr_db, cellroot, "target_ul_sinr", -1));
HANDLEPARSERCODE(parse_default_field(cell_cfg.enable_phr_handling, cellroot, "enable_phr_handling", false));
if (cellroot.exists("ho_active") and cellroot["ho_active"]) {
HANDLEPARSERCODE(parse_meas_cell_list(&cell_cfg.meas_cfg, cellroot["meas_cell_list"]));

2
srsenb/src/stack/mac/sched_ue.cc
Unescape Escape View File

@ -1323,7 +1323,7 @@ cc_sched_ue::cc_sched_ue(const sched_interface::ue_cfg_t& cfg_,
ue_cc_idx(ue_cc_idx_),
last_tti(current_tti),
harq_ent(SCHED_MAX_HARQ_PROC, SCHED_MAX_HARQ_PROC),
tpc_fsm(cell_cfg_.nof_prb(), cell_cfg_.cfg.target_ul_sinr)
tpc_fsm(cell_cfg_.nof_prb(), cell_cfg_.cfg.target_ul_sinr, cell_cfg_.cfg.enable_phr_handling)
{
dl_cqi_rx = false;
dl_cqi = (ue_cc_idx == 0) ? cell_params->cfg.initial_dl_cqi : 0;

11
srsenb/src/stack/rrc/rrc.cc
Unescape Escape View File

@ -612,11 +612,12 @@ void rrc::config_mac()
item.si_window_ms = cfg.sib1.si_win_len.to_number();
item.prach_rar_window =
cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.ra_supervision_info.ra_resp_win_size.to_number();
item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset;
item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx;
item.enable_64qam = cfg.sibs[1].sib2().rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam;
item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi;
item.target_ul_sinr = cfg.cell_list[ccidx].target_ul_sinr_db;
item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset;
item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx;
item.enable_64qam = cfg.sibs[1].sib2().rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam;
item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi;
item.target_ul_sinr = cfg.cell_list[ccidx].target_ul_sinr_db;
item.enable_phr_handling = cfg.cell_list[ccidx].enable_phr_handling;
item.nrb_pucch = SRSLTE_MAX(cfg.sr_cfg.nof_prb, cfg.cqi_cfg.nof_prb);
rrc_log->info("Allocating %d PRBs for PUCCH\n", item.nrb_pucch);

1
srsenb/test/mac/sched_test_rand.cc
Unescape Escape View File

@ -271,6 +271,7 @@ sched_sim_events rand_sim_params(uint32_t nof_ttis)
sim_gen.sim_args.cell_cfg = {generate_default_cell_cfg(nof_prb)};
sim_gen.sim_args.cell_cfg[0].target_ul_sinr = pick_random_uniform({10, 15, 20, -1});
sim_gen.sim_args.cell_cfg[0].enable_phr_handling = false;
sim_gen.sim_args.default_ue_sim_cfg.ue_cfg = generate_default_ue_cfg();
sim_gen.sim_args.default_ue_sim_cfg.periodic_cqi = true;
sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.maxharq_tx = std::uniform_int_distribution<>{1, 5}(srsenb::get_rand_gen());

4
srsenb/test/mac/sched_tpc_test.cc
Unescape Escape View File

@ -26,7 +26,7 @@ int test_finite_target_snr()
const uint32_t nof_prbs = 50;
const int target_snr = 15;
tpc tpcfsm(nof_prbs, 15);
tpc tpcfsm(nof_prbs, 15, true);
// TEST: While no SNR info is provided, no TPC commands are sent
for (uint32_t i = 0; i < 100; ++i) {
@ -71,7 +71,7 @@ int test_undefined_target_snr()
{
const uint32_t nof_prbs = 50;
tpc tpcfsm(nof_prbs);
tpc tpcfsm(nof_prbs, -1, true);
TESTASSERT(tpcfsm.max_ul_prbs() == 50);
// TEST: While the PHR is not updated, a limited number of TPC commands should be sent

Write Preview
Loading…
Cancel
Save