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// All times are in ms. Use -1 for infinity, where available
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// 4G Section
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// srb1_config = {
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// rlc_config = {
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// ul_am = {
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// sn_field_len = 12;
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// t_poll_retx = 45;
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// poll_pdu = -1;
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// poll_byte = -1;
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// max_retx_thresh = 4;
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// };
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// dl_am = {
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// sn_field_len = 12;
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// t_reassembly = 50;
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// t_status_prohibit = 50;
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// };
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// };
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// }
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// srb2_config = {
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// rlc_config = {
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// ul_am = {
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// sn_field_len = 12;
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// t_poll_retx = 45;
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// poll_pdu = -1;
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// poll_byte = -1;
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// max_retx_thresh = 4;
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// };
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// dl_am = {
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// t_reordering = 35;
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// t_status_prohibit = 0;
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// };
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// };
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// }
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qci_config = (
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{
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qci = 7;
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pdcp_config = {
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discard_timer = -1;
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pdcp_sn_size = 12;
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}
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rlc_config = {
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ul_um = {
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|
sn_field_length = 10;
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|
};
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|
|
dl_um = {
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|
|
sn_field_length = 10;
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t_reordering = 45;
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};
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};
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logical_channel_config = {
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priority = 13;
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prioritized_bit_rate = -1;
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|
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bucket_size_duration = 100;
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log_chan_group = 2;
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};
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|
enb_specific = {
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|
dl_max_retx_thresh = 32;
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|
};
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|
|
},
|
|
|
|
{
|
|
|
|
qci = 9;
|
|
|
|
pdcp_config = {
|
|
|
|
discard_timer = 150;
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|
|
|
status_report_required = true;
|
|
|
|
}
|
|
|
|
rlc_config = {
|
|
|
|
ul_am = {
|
|
|
|
t_poll_retx = 120;
|
|
|
|
poll_pdu = 64;
|
|
|
|
poll_byte = 750;
|
|
|
|
max_retx_thresh = 16;
|
|
|
|
};
|
|
|
|
dl_am = {
|
|
|
|
t_reordering = 50;
|
|
|
|
t_status_prohibit = 50;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
logical_channel_config = {
|
|
|
|
priority = 11;
|
|
|
|
prioritized_bit_rate = -1;
|
|
|
|
bucket_size_duration = 100;
|
|
|
|
log_chan_group = 3;
|
|
|
|
};
|
|
|
|
enb_specific = {
|
|
|
|
dl_max_retx_thresh = 32;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
);
|
|
|
|
|
|
|
|
// 5G Section
|
|
|
|
// srb1_5g_config = {
|
|
|
|
// rlc_config = {
|
|
|
|
// ul_am = {
|
|
|
|
// sn_field_len = 12;
|
|
|
|
// t_poll_retx = 50;
|
|
|
|
// poll_pdu = 4;
|
|
|
|
// poll_byte = 3000;
|
|
|
|
// max_retx_thres = 4;
|
|
|
|
// };
|
|
|
|
// dl_am = {
|
|
|
|
// sn_field_len = 12;
|
|
|
|
// t_reassembly = 50;
|
|
|
|
// t_status_prohibit = 50;
|
|
|
|
// };
|
|
|
|
// };
|
|
|
|
// }
|
|
|
|
|
|
|
|
// srb2_5g_config = {
|
|
|
|
// rlc_config = {
|
|
|
|
// ul_am = {
|
|
|
|
// sn_field_len = 12;
|
|
|
|
// t_poll_retx = 50;
|
|
|
|
// poll_pdu = 4;
|
|
|
|
// poll_byte = 3000;
|
|
|
|
// max_retx_thres = 4;
|
|
|
|
// };
|
|
|
|
// dl_am = {
|
|
|
|
// sn_field_len = 12;
|
|
|
|
// t_reassembly = 50;
|
|
|
|
// t_status_prohibit = 50;
|
|
|
|
// };
|
|
|
|
// };
|
|
|
|
// }
|
|
|
|
|
|
|
|
five_qi_config = (
|
|
|
|
{
|
|
|
|
five_qi = 7;
|
|
|
|
pdcp_nr_config = {
|
|
|
|
drb = {
|
|
|
|
discard_timer = 50;
|
|
|
|
pdcp_sn_size_ul = 18;
|
|
|
|
pdcp_sn_size_dl = 18;
|
|
|
|
};
|
|
|
|
t_reordering = 50;
|
|
|
|
};
|
|
|
|
rlc_config = {
|
|
|
|
um_bi_dir = {
|
|
|
|
ul_um = {
|
|
|
|
sn_field_len = 12;
|
|
|
|
};
|
|
|
|
dl_um = {
|
|
|
|
sn_field_len = 12;
|
|
|
|
t_reassembly = 50;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
},
|
|
|
|
{
|
|
|
|
five_qi = 9;
|
|
|
|
pdcp_nr_config = {
|
|
|
|
drb = {
|
|
|
|
discard_timer = 50;
|
|
|
|
pdcp_sn_size_ul = 18;
|
|
|
|
pdcp_sn_size_dl = 18;
|
|
|
|
};
|
|
|
|
t_reordering = 50;
|
|
|
|
};
|
|
|
|
rlc_config = {
|
|
|
|
am = {
|
|
|
|
ul_am = {
|
|
|
|
sn_field_len = 12;
|
|
|
|
t_poll_retx = 50;
|
|
|
|
poll_pdu = 4;
|
|
|
|
poll_byte = 3000;
|
|
|
|
max_retx_thres = 4;
|
|
|
|
};
|
|
|
|
dl_am = {
|
|
|
|
sn_field_len = 12;
|
|
|
|
t_reassembly = 50;
|
|
|
|
t_status_prohibit = 50;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
}
|
|
|
|
);
|
|
|
|
|